Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-14
2011-06-14
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S729000, C714S741000
Reexamination Certificate
active
07962822
ABSTRACT:
A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus200generating an initial test vector set216for a logic circuit includes a target vector identification unit204identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set216, and a test vector set conversion unit206converting the test vector identified by the test vector identification unit204and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.
REFERENCES:
patent: 5930149 (1999-07-01), Takahashi
patent: 6067651 (2000-05-01), Rohrbaugh et al.
patent: 6751767 (2004-06-01), Toumiya
patent: 6986090 (2006-01-01), Hathaway et al.
patent: 7027947 (2006-04-01), Maruyama
patent: 7188287 (2007-03-01), Matsuda et al.
patent: 7428681 (2008-09-01), Kang et al.
patent: 7509550 (2009-03-01), Rajski et al.
patent: 2009/0083593 (2009-03-01), Wen et al.
patent: 2009/0249147 (2009-10-01), Rajski et al.
Miyase et al., Don't-Care Identification Specific Bits of Test Patterns, 2002, IEEE, pp. 1-6.
Wen et al., A new ATPG method for efficient capture power reduction during scan testing, Apr. 30, 2006, IEEE, pp. 1-6.
Wang, LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation, 1999, IEEE, paper4.2, pp. 85-94.
Li et al., On Reducing Peak Current and Power During Test, 2005, IEEE, pp. 1-6.
Wen et al., Low-Capture-Power Test Generation for Scan-Based At-Speed Testing, 2005, IEEE, pp. paper 39.2, 1-10.
Butler et al., Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques, 2004, IEEE, Paper 12.4, pp. 355-364.
Rosinger et al., Scan architecture with mutally exclusive scan segment activation for shift- and capture-power reduction, Jul. 2004, IEEE, vol. 23 Issue: 7, pp. 1142-1153.
Wang et al., ATPG for Heat Dissipation Minimization During Test Application, Feb. 1998, IEEE Transactions on Computers, vol. 47, No. 2, pp. 256-262.
Wang et al., An Automatic Test Pattern Generator for Minimizing Switching Activity During Scan Testing Activity, Aug. 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 8, pp. 954-.
International Search Report for PCT/JP2007/056149 dated Jun. 12, 2007.
Date Hiroshi
Kajihara Seiji
Minamoto Yoshihiro
Miyase Kohei
Wen Xiaoqing
Japan Science & Technology Agency
Kyushu Institute of Technology
Rankin , Hill & Clark LLP
System JD Co., Ltd.
Tabone, Jr. John J
LandOfFree
Generating device, generating method, program and recording... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Generating device, generating method, program and recording..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating device, generating method, program and recording... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2623765