Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-07-29
2001-05-15
Decady, Albert (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S341000
Reexamination Certificate
active
06233714
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the maximum likelihood (ML) detection of binary-coded sequences derived from run-length-limited (RLL) partial response analog waveforms. These waveforms are used in disk recording channels and the like. More particularly, the invention relates to a generalized method and means for defining and operating ML detectors for any particular type of [d, k] partial response channel or waveform.
DESCRIPTION OF RELATED ART
One result of digital information processing is the production of binary-coded sequences. When the sequences are to be stored on a disk drive or the like, it is customary to first add additional bits representing an error correction coding (ECC) artifact. Next, the sequences are sent through a run-length-limited (RLL) or modulation encoder and a partial response (PR) channel. The modulation encoder and partial response channel are designed to impart clocking information to the binary sequence and to transform this enriched sequence into a highly recoverable analog pattern when read back from the storage medium. The actual recorded signals on a disk drive track are Gaussian-shaped peaks and valleys varying over time.
When the recorded signals are read back, it is necessary to invert the process. In this regard, recorded signals are first applied to a PR decoder or detector. The PR detector output is in the form of a binary-coded sequence enriched with the modulation code and the ECC artifact. The former is stripped off by the RLL or modulation decoder. The result is then applied to an ECC decoder for any necessary error detection and correction.
The present magnetic storage track recording environment is characterized by high signal density, intersymbol interference (ISI), and white Gaussian noise. PR is the current response to increasing densities and speed, and replaces peak detection as the method of choice.
PR detection comprises two parts. These are ascertaining the PR signal from the storage medium and assigning the actual PR signal to a binary sequence on a maximum likelihood basis. That is, a binary sequence is correlated with a valid PR signal to which a detected signal is most closely associated. In this regard, the permissible PR signals having the noise-free and signal space location attributes can be determined in advance. Thus, when an actual PR signal encrusted with some noise is detected, its location (Euclidean distance) with respect to the location of every one of the permissible signals can be resolved based on the shortest or minimum distance.
As used in this specification, the term “distance” connotes Euclidean distance d
2
rather than the code theory term “Hamming” distance. The Euclidean distance metric d
2
is the sum of the squares of the differences between a pair of vectors. If a reference waveform produces a vector of sample values [x
1
x
2
x
3
x
4
] and a readback waveform yields values taken at the sample times of [y
1
y
2
y
3
y
4
], then the Euclidean distance d
2
is taken to be
d
2
=&Sgr;(
x
1
−y
1
)
2
+(
x
2
−y
2
)
2
+ . . . +(
x
n
−y
n
)
2
.
The PR detector comprises a signal sampler and an ML detector. In this regard, the PR signal is sampled one or more times at a predetermined self-clocked rate. This set of samples is termed a “vector of samples” and is then applied to a Viterbi or equivalent detector. The Viterbi detector is a well-known finite state machine (FSM) configured to process samples. It resolves a noisy sample to the closest one of the nominal or “known” nonnoisy samples using traversal of a special purpose directed graph called a trellis. Such processing is described in Fettweis et al., U.S. Pat. No. 5,430,744, “Method and Means for Detecting Partial Response Waveforms Using a Modified Dynamic Programming Heuristic”, issued Jul. 4, 1995. Unfortunately, the trellis processing, as exemplified in Fettweis, is complex in function, structure, and operation and costly.
There have been other approaches to processing RLL or (d, k) constrained PR waveforms. These have been of the finite lookahead decision feedback ML detector type. For instance, Patel, U.S. Pat. No. 4,945,538, entitled “Method and Apparatus for Processing Sample Values in a Coded Signal Processing Channel”, issued Jul. 31, 1990, sought to reduce the complexity of trellis-based, bit-by-bit detection. Patel assumed that most errors in reading from a [d, k] partial response channel are due to peaks shifted by one clock period or cycle.
In general, Patel's solution was the use of a linear filter in his lookahead decision feedback FSM to increase the Euclidean distance between events for a (1, 7) EPR4-coded channel. The [d, k]=(1, 7) means that there is inserted at least one “0” and not more than seven “0's” between a pair of consecutive “1's” in any binary sequence. An EPR4 type of partial response signal means that the nominal or noise-free signal, if sampled at the Nyquist rate, would yield relative magnitudes 1-2-1 at those sample times. This means that there exists a “target waveform” of a peak shape that has been “equalized”. If the equalized target waveform were sampled at its Nyquist frequency, then three samples would be obtained at three clock times during its excursus. The waveform at the sample times should have magnitudes respectively of 1, 2, and 1.
Hassner, U.S. Pat. No. 5,638,065, “Maximum-likelihood Symbol Detection for RLL-coded Data”, issued Jun. 10, 1997, is directed to binary sequence ML detection of waveforms from a (1, 7) E
2
PR4 channel. This PR waveform is sampled four times with a nominal relative amplitude of 1-3-3-1. Whereas Patel is limited to detecting one bit at any time, Hassner modified Patel's FSM to detect bits in parallel (actually four bits/cycle) or one symbol at a time. While Hassner utilizes the linear filter and bit clock of the Patel '538 patent, he additionally utilizes a symbol clock.
Jeon et al., “Systematic Approach to Signal Space Detection”,
IEEE Transactions on Magnetics
, Vol. 33, No. 5, September 1997, pp. 2737-2739, emphasize the use of a finite delay decision tree (FDTS) in their finite lookahead decision feedback (FSM) detector. The FDTS operates as a form of signal space partitioning and as an approximation to the Viterbi detector. Conceptually, Moon's nominal sample values are mapped into an N-dimensional space. Hyperplanes are passed through this N-dimensional space, thereby partitioning the nominal sample values according to predetermined criteria. As embodied in a detector, the estimation of one or more detected samples in this N-space is then made using the nearest neighbor rule (minimal Euclidean distance).
SUMMARY OF THE INVENTION
It is accordingly an object of this invention to devise a method and apparatus for defining and operating a partial response detector for any given partial wave shape h, [d, k] RLL modulation code, minimum Euclidean distance d
2
min
of [d, k] coded PR wave, and minimum Euclidean distance d
2
spec
≦d
2
min
specified for PR detector performance.
It is still another object that such method and apparatus for defining and operating a [d, k] PR detector be utilizable by [d, k] PR waves of the PR4, EPR4, and E
2
PR4 types and the like.
It is yet another object that such method and apparatus exhibit less operational and structural complexity than that exhibited by a Viterbi-type trellis PR detector.
The foregoing objects are believed satisfied by a method and apparatus in which logic equations governing PR detector operations are first defined from a predetermined set of parameters comprising the PR shape h, [d, k] RLL code, d
2
min
, and d
2
spec
≦d
2
min
. The definition of the PR detector is expressed in a series of logic equations involving a linear decision function integer matrix H, a vector of threshold values t, and decision logic F. A processor is then configured according to the equations to emulate the defined (d, k) PR detector for sampling,
Hassner Martin Aureliano
Heise Nyles
Brodie R. Bruce
De'cady Albert
International Business Machines - Corporation
Lamarre Guy
McSwain Marc D.
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