General-purpose customizable memory controller

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules

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711105, G06F 1200

Patent

active

059182423

ABSTRACT:
A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations into generic memory instructions and translates the logical addresses into physical addresses. The memory instruction decoder further converts the generic memory instructions into memory specific control signals and converts the physical addresses into actual memory specific addresses. This design permits the memory instruction processor to be designed and finalized before an actual memory type is selected for system use at which time the less complex memory instruction decoder can be designed.

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"Programmable Memory Controller" Feb., 89, IBM Technical Disclosure Bulletin, (pp. 351-354).

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