Gated scan output flip-flop

Details Gated scan output flip-flop Gated scan output flip-flop

2005-02-08

2005-02-08

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S046000, C327S202000

Reexamination Certificate

active

06853212

ABSTRACT:
A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.

REFERENCES:
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patent: 5592493 (1997-01-01), Crouch et al.
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patent: 5719878 (1998-02-01), Yu et al.
patent: 5831993 (1998-11-01), Graef
patent: 5881067 (1999-03-01), Narayanan et al.
patent: 5886901 (1999-03-01), Magoshi
patent: 6114892 (2000-09-01), Jin
patent: 6680622 (2004-01-01), Zounes

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