Gated diode nonvolatile memory process

Details Gated diode nonvolatile memory process Gated diode nonvolatile memory process

2006-05-31

2009-02-17

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21053

Reexamination Certificate

active

07491599

ABSTRACT:
A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

REFERENCES:
patent: 4569120 (1986-02-01), Stacy et al.
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 5365083 (1994-11-01), Tada
patent: 5483484 (1996-01-01), Endoh et al.
patent: 5617357 (1997-04-01), Haddad et al.
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 5753950 (1998-05-01), Kojima
patent: 5768192 (1998-06-01), Eitan
patent: 5814853 (1998-09-01), Chen
patent: 5912840 (1999-06-01), Gonzalez et al.
patent: 6008525 (1999-12-01), Barron et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6160286 (2000-12-01), Chi
patent: 6351411 (2002-02-01), Forbes et al.
patent: 6436769 (2002-08-01), Kanamori
patent: 6510082 (2003-01-01), Le et al.
patent: 6580124 (2003-06-01), Cleeves et al.
patent: 6614686 (2003-09-01), Kawamura
patent: 6631085 (2003-10-01), Kleveland et al.
patent: 6639836 (2003-10-01), Hung et al.
patent: 6646914 (2003-11-01), Haddad et al.
patent: 6657894 (2003-12-01), Yeh et al.
patent: 6670240 (2003-12-01), Ogura et al.
patent: 6690601 (2004-02-01), Yeh et al.
patent: 6771543 (2004-08-01), Wong et al.
patent: 6808986 (2004-10-01), Rao et al.
patent: 6826080 (2004-11-01), Park et al.
patent: 6862216 (2005-03-01), Hopper et al.
patent: 6873004 (2005-03-01), Han et al.
patent: 6888750 (2005-05-01), Walker et al.
patent: 6996011 (2006-02-01), Yeh et al.
patent: 7072219 (2006-07-01), Yeh
patent: 2002/0167844 (2002-11-01), Han et al.
patent: 2003/0032243 (2003-02-01), Ogura et al.
Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” Electron Devices Meeting, 2002. IEDM '02. Digest. International, Dec. 8-11, 2002, pp. 931-934.

Affiliated with

Also associated with

Rating

Gated diode nonvolatile memory process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gated diode nonvolatile memory process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gated diode nonvolatile memory process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4092425