Gate-to-drain overlapped MOS transistor fabrication process and

Details Gate-to-drain overlapped MOS transistor fabrication process and Gate-to-drain overlapped MOS transistor fabrication process and

1993-09-03

1997-04-15

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257387, 257408, 257413, H01L 2976

Patent

active

056212364

ABSTRACT:
A method for fabricating a gate-to-drain overlapped MOS transistor in which gate-to-drain capacitance is lower and a structure thereby. A pad oxide layer is formed over a substrate having a first conductive layer with a first pattern formed on a first gate oxide layer, and etchback process is performed until surface part and a predetermined upper parts of the both side walls of the first conductive layer is exposed. As a result, a second conductive layers with a second pattern is formed and a second gate oxide layer thicker than the first gate oxide layer is formed.

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patent: 5120673 (1992-06-01), Itoh
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patent: 5159417 (1992-10-01), Ozaki
patent: 5214305 (1993-05-01), Huang et al.
Silicon-Gate LOCOS NMOS Proccess, "Modem MOS Technology", Section 7-4, pp. 138-143, Jan. 1990.

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