Gate straining in a semiconductor device

Details Gate straining in a semiconductor device Gate straining in a semiconductor device

2007-05-24

2009-11-03

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C257SE21409, C257SE21632

Reexamination Certificate

active

07611935

ABSTRACT:
Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive vias are formed in TEOS oxide regions surrounding the sidewall spacers of a metal gate structure, where the metal gate structure includes compressive nitride material within the gate opening. After forming the conductive vias the remaining TEOS oxide is removed and tensile nitride material is deposited between the sidewall spacers and the conductive vias. The sidewall spacers serve as retaining walls for the tensile nitride material, which preserves the tensile characteristics of the material. A similar fabrication technique is utilized to form a PMOS device. For a PMOS device, however, the metal gate structure includes tensile nitride material within the gate opening, and compressive nitride material between the sidewall spacers and the conductive vias.

REFERENCES:
patent: 5895955 (1999-04-01), Gardner et al.
patent: 6596623 (2003-07-01), Subramanian et al.
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2004/0058499 (2004-03-01), Ishitsuka et al.
patent: 2005/0087870 (2005-04-01), Adetutu et al.
patent: 2005/0156199 (2005-07-01), Ko et al.
patent: 2005/0214998 (2005-09-01), Chen et al.
patent: 2007/0048958 (2007-03-01), Liao et al.
patent: 2007/0063286 (2007-03-01), Kotani
patent: 2008/0083955 (2008-04-01), Kanarsky et al.
patent: 2008/0217665 (2008-09-01), Chen et al.
patent: 2008/0258234 (2008-10-01), Henson et al.

Affiliated with

Also associated with

Rating

Gate straining in a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate straining in a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate straining in a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4139240