Gate stack for high performance sub-micron CMOS devices

Details Gate stack for high performance sub-micron CMOS devices Gate stack for high performance sub-micron CMOS devices

2001-07-16

2003-07-22

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06596599

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a gate electrode for CMOS devices having sub-micron channel length.
(2) Description of the Prior Art
CMOS devices, which form the essential components of DRAM cells, are typically created using overlying layers of semiconductor material with the lowest layer being a layer of pad oxide and the highest layer being a layer of silicided material that serves as low resistivity electrical contact to the gate electrode. A gate electrode is typically created overlying the layer of pad oxide, this layer is also referred to as gate dielectric or gate stack adopting oxide. Current technology for the creation of CMOS devices uses a silicon dioxide layer as the gate dielectric for CMOS devices. With a sharp reduction in device feature size, the thickness of the layer of gate dielectric must also be reduced, for the era of device features in the sub-micron range the gate thickness is approaching 2 nanometers or less. A continued reduction of the thickness of the layer of gate dielectric leads to increasing the tunneling current through this thin layer of gate dielectric. For this reason a thin layer of silicon dioxide (thinner than about 1.5 nm) cannot be used as the gate dielectric for CMOS devices having sub-micron device dimensions.
A concerted effort is underway in the industry to provide materials that can be used for a gate dielectric of a gate electrode. These materials must have a high dielectric constant, which allows for the layer of gate dielectric to be thicker while maintaining device performance and also reducing the tunneling current through the layer of gate dielectric. The dielectric constant of the searched for materials is measured with respect to the dielectric constant of silicon dioxide, since silicon dioxide has for past device creations formed the dielectric of choice for the gate dielectric. The range of dielectric constants varies between about 3.9 for silicon dioxide and about 10 for high-k dielectric layers. Other materials that can be cited in this respect include ZrO
2
with a dielectric constant of about 25, HfO
2
with a dielectric constant of about 30 and Al
2
O
3
with a dielectric constant of about 25.
The MOSFET device is one of the most widely used devices in the semiconductor industry and forms an integral part of most semiconductor devices. The MOSFET device comprises, in its simplest form, a three-terminal device with electrical contacts being provided to the source/drain regions and the gate electrode of the device. A channel region is formed in the substrate underlying the gate electrode, the channel region connects the source region (in the surface of the substrate) with the drain region, also in the surface of the substrate.
Increased miniaturization of semiconductor devices creates a host of complex issues that must be addressed in order to maintain device performance. The conventional approach of using a layer of silicon oxide, over which the gate electrode is created, and of using silicon nitride for the gate spacers creates problems of scaling of the thickness of the layer of gate oxide (due to excessive leakage current, which is induced by direct tunneling) and scaling of the spacer width (due to the increased coupling capacitance and the reduced insulation between the gate electrode and the source/drain regions of the structure). The invention addresses these concerns and provides a method in which an air gap spacer is provided combined with a polysilicon-Ge gate or a pre-doped polysilicon-silicon gate.
U.S. Pat. No. 6,110,790 (Chen) shows a gate with an air gap spacer.
U.S. Pat. No. 6,194,748 (Yu) shows a gate stack with a high K gate dielectric and low-k spacers.
U.S. Pat. No. 5,990,532 (Gardner) shows a method for creating an air gap under the gate by an etch back of the gate dielectric and an air sealing deposition.
U.S. Pat. No. 5,864,160 (Buynoski) shows a gate with an air gap on one side and a sealing step.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths.
Another objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths whereby scaling issues of the gate oxide of the device are addressed.
Yet another objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths whereby air-gap spacers are combined with selected gate dielectrics.
A still further objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths of increased drive current capability.
A still further objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths of reduced parasitic capacitance impact.
In accordance with the objectives of the invention a new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.


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F. Boeuf et al., “16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation,” 2001, IEEE.

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