Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2011-01-11
2011-01-11
Menz, Douglas M (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C438S585000
Reexamination Certificate
active
07868410
ABSTRACT:
A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.
REFERENCES:
patent: 1949131 (1934-02-01), Shields
patent: 3320484 (1967-05-01), Riley et al.
patent: 3634203 (1972-01-01), McMahon et al.
patent: 3827949 (1974-08-01), Platter et al.
patent: 4459739 (1984-07-01), Shepherd et al.
patent: 4460413 (1984-07-01), Hirata et al.
patent: 4564720 (1986-01-01), Hogan
patent: 5032237 (1991-07-01), Wieserman et al.
patent: 5071517 (1991-12-01), Oabayashi
patent: 5196361 (1993-03-01), Ong et al.
patent: 5342501 (1994-08-01), Okabayashi
patent: 6224735 (2001-05-01), Akutsu et al.
patent: 6309969 (2001-10-01), Oskam et al.
patent: 6686282 (2004-02-01), Simpson et al.
patent: 6707100 (2004-03-01), Gajda
patent: 6797145 (2004-09-01), Kosowsky
patent: 6899815 (2005-05-01), Coomer et al.
patent: 7105886 (2006-09-01), Droopad
patent: 2003/0155246 (2003-08-01), Schimmel et al.
patent: 2003/0201442 (2003-10-01), Makita
patent: 2004/0203181 (2004-10-01), Shang et al.
patent: 2005/0003612 (2005-01-01), Hackler et al.
Ishikawa Y. et al., “Electrodeposition of Ti02photocatalyst into porous alumite prepared in phosphoric acid,” Solid State Ionics, vol. 151, No. 1-4, pp. 213-218, 2002.
Paily R. et al., “Improvement in Electrical Characteristics of Ultrathin Thermally Grown SiO2by Selective Anodic Oxidation,” IEEE Electron Device Letters, vol. 23, No. 12, pp. 707-709, 2002.
Bhandary U. et al., “Replacement Metal-Gate NMOSFETs With ALD TaN/EP-Cu, PVD Ta. and PVD TaN Electrode,” IEEE Electron Device Letters, IEEE Servce Center, vol. 24, No. 5, pp. 304-305, 2003.
Uno S. et al., “Fabrication of high performance InP MESFETs with in-situ pulse-plated metal gates,” Indium Phosphide and Related Materials, 1996. IPRM '96., Eith International Conference on Schwabisch-gmund, Germany Apr. 21-25, 1996, IEEE, US, pp. 338-341, 1996.
Search Report in counterpart European application 05852630.2-2203.
Basker Veeraraghavan S.
Cabral, Jr. Cyril
Cooper Emanuel I.
Deligianni Hariklia
Frank Martin M.
Connolly Bove & Lodge & Hutz LLP
International Business Machines - Corporation
Menz Douglas M
Percello Louis J.
LandOfFree
Gate stack engineering by electrochemical processing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate stack engineering by electrochemical processing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate stack engineering by electrochemical processing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2630663