Gate processing method with reduced gate oxide corner and...

Details Gate processing method with reduced gate oxide corner and... Gate processing method with reduced gate oxide corner and...

2001-09-28

2003-12-02

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S294000, C438S296000, C438S424000, C438S585000, C257S333000

Reexamination Certificate

active

06656798

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the manufacture of semiconductor gates, more specifically to the reduction of oxide thinning at the corners and edges of gate oxides.
BACKGROUND OF THE INVENTION
Gate oxide reliability is often limited by gate oxide thinning at the STI (shallow trench isolation) edges and corners. The reason for this effect is the insufficient STI corner rounding during AA oxidation and the orientation-dependent and stress-induced gate oxidation around these edges. The typical prior art process is shown in
FIGS. 1
a
through
1
e.
Referring to
FIG. 1
a,
we see a gate structure
1
comprising a pad oxide layer, sandwiched between a pad nitride layer
3
and a silicon substrate
4
.
Referring to
FIG. 1
b,
we see that the pad nitride layer
3
is pulled back. Typical values of the pad nitride pullback are from 0 to 30 nm. The nitride pullback is done by using selective wet chemical etch of the pad nitride.
Referring to
FIG. 1
c,
the next steps in the processing are the oxidation of the exposed silicon (active area, or “AA”, oxidation) and an STI fill with a dielectric, usually oxide.
Referring to
FIG. 1
d,
the pad nitride
3
is then stripped. This strip is selected to the oxide
5
, although it etches a small part of it. Typical etch selectivities are 1 to 50. For 100 nm of nitride that gives 2 nm of sideways oxide etch. This is followed by an etch of the pad oxide
2
. With some overetch, this etch also extends sideways into the STI isolation oxide
5
. For a typical pad oxide thickness of 5 nm, this gives a sideways etch of 5 to 7 nm. The pad oxide etch is followed by sacrificial oxidation to create a thin oxide with well-defined thickness and uniformity. This oxide is needed as a screen oxide for implants.
The situation at this point is depicted in
FIG. 1
d.
The thickness of the sacrificial oxide
6
is typically 5 nm to 10 nm.
Referring to
FIG. 1
e,
after the implants, the sacrificial oxide is stripped using wet chemical oxide etch selective to nitride. Again using a slight overetch, approximately 10 nm of oxide are etched sideways into the STI. This sideways etch is sometimes even larger depending on the densification of the oxide used for the STI fill. This step leads to the exposure of the STI edge. In the following gate oxidation, the gate oxide
7
is usually thinner at the edges, especially the corners, as compared to the center. The reason is believed to be the orientation dependent oxidation rate and, to a larger extent, mechanical stress.
SUMMARY OF THE INVENTION
Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure comprising a semiconductor gate capped with a pad oxide layer bounded by one or more isolation trenches filled with silicon oxide, providing a sacrificial oxide layer by thickening said pad oxide layer to a thickness effective in using said thickened pad oxide layer as said sacrificial oxide layer, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a gate oxide layer.
In another aspect of the invention said thickening step comprises heating said semiconductor wafer in an oxygen-containing atmosphere to a temperature effective in silicon oxide growth.
In another aspect of the invention said semiconductor wafer is heated to a temperature of from about 500° C. to about 1,000° C.
In another aspect of the invention said temperature is about 700° C.
In another aspect of the invention said semiconductor wafer is heated for about one hour.
In another aspect of the invention said sacrificial oxide layer is from about 20 to about 100 angstroms thick.
In another aspect of the invention said sacrificial oxide layer is from about 30 to about 50 angstroms thick.
In another aspect of the invention said sacrificial oxide layer is about 40 angstroms thick.
In another aspect of the invention said sacrificial oxide layer comprises amorphous silicon oxide.
Disclosed is a semiconductor structure comprising a semiconductor gate capped with a sacrificial oxide layer bounded by one or more isolation trenches, and said sacrificial oxide layer comprises amorphous silicon oxide.
In another aspect of the apparatus said sacrificial oxide layer is between about 20 to about 100 angstroms thick.
In another aspect of the apparatus said sacrificial oxide layer is between about 30 to about 50 angstroms thick.
In another aspect of the apparatus said sacrificial oxide layer is about 40 angstroms thick.


REFERENCES:
patent: 6087243 (2000-07-01), Wang
patent: 6309924 (2001-10-01), Divakaruni et al.
patent: 6342431 (2002-01-01), Houlihan et al.
patent: 6391720 (2002-05-01), Sneelal et al.
patent: 6437381 (2002-08-01), Gruening et al.

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