Gate process and gate structure for an embedded memory device

Details Gate process and gate structure for an embedded memory device Gate process and gate structure for an embedded memory device

2005-07-12

2005-07-12

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06916702

ABSTRACT:
A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

REFERENCES:
patent: 6258667 (2001-07-01), Huang
patent: 6509235 (2003-01-01), Chien et al.
patent: 6589841 (2003-07-01), Pham et al.
patent: 6670227 (2003-12-01), Thio et al.
patent: 6798015 (2004-09-01), Kasuya
patent: 2002/0132458 (2002-09-01), Chien et al.

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