Gate prespacers for high density, high performance DRAMs

Details Gate prespacers for high density, high performance DRAMs Gate prespacers for high density, high performance DRAMs

2000-06-22

2001-12-04

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S595000, C438S700000

Reexamination Certificate

active

06326260

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor memory devices and, more particularly, to a method of forming a gate conductor for a dynamic random access memory (DRAM) structure wherein spacers (hereinafter referred to as prespacers) are formed prior to completely etching the gate conductor and wherein the thickness of the oxide layers in the array and support regions of the structure are varied so as to improve device performance.
BACKGROUND OF THE INVENTION
In semiconductor memory device manufacturing, the channel length of the DRAM transfer gate devices continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for low leakage DRAM transfer devices. There is thus a need for novel integration schemes with only limited shrinking of the channel length.
As the DRAM cell size decreases, the transfer gate has consequently shrunk with it. Earlier cell sizes (>8 F
2
) allow for wiggled gates to keep the array transistor off leakage to a minimum. With the onset of 8 F
2
cells with equal lines and spaces at minimum feature size, F, in the wordline direction, there is need to provide larger transfer gate lengths of the array pass transistor by non-lithographic techniques. Conventional scaling techniques use shallow junctions (limited by surface leakage and charge writeback characteristics), high channel doping concentrations or halo implants which increase leakage and are thus not easy to incorporate in DRAM processing.
One known process is based on the BEST (BuriEd Strap) cell modified for 8 F
2
. Once the trench capacitor and shallow trench isolation are formed, the gate conductor stack is put down. Typically, the gate conductor stack consists of polysilicon and WSi
x
capped with SiN. During the gate mask opening step, the SiN is patterned and the etch typically stops in the WSi
x
, the resist is stripped and the remaining gate conductor stack is etched with the SiN as a hard mask. Post gate sidewall oxidation, the SiN spacers are formed, followed by a barrier SiN film and boron phosphorus silicate glass (BPSG) deposition, densification and planarization. A TEOS (tetraethylorthosilicate) layer is formed for the damascene bitlines and the bitline contacts are etched borderless to the gates prior to forming the bitline wiring layer (generally tungsten).
Additionally, it is known that the present processing of DRAM structures in the array portion of the device directly links the lithographic dimension to the polysilicon linewidth. Hence, if there is resist webbing, the increase in the polysilicon linewidth is limited which directly affects the retention of the DRAM cell.
The present invention is thus directed to further improvements in gate conductor processing which can be easily incorporated into existing DRAM processing techniques.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of manufacturing a gate conductor of a memory device wherein the length of the gate polysilicon can be tailored so as to improve the retention of the DRAM cell.
Another object of the present invention is to provide a method of manufacturing a gate conductor of a memory device wherein the length of the gate polysilicon can be tailored so as to reduce array off-state leakage.
A yet further object of the present invention is to provide a method of manufacturing a gate conductor which can be easily implemented into existing DRAM processing techniques.
A still further object of the present invention is to provide a method of manufacturing sub-8 F
2
memory devices in which the method of the present invention can be employed in fabricating the gate conductor.
Further objects of the present invention are to form two different sidewall oxide thicknesses without increasing the thermal budget of the process and to achieve the differential oxide thicknesses without the need of utilizing a critical mask.
These and other objects and advantages are achieved in the present invention by forming prespacers on the sidewalls of the gate conductor prior to completely etching the gate conductor stack. Specifically, the method of the present invention, which achieves all of the above-mentioned objects, while overcoming the drawbacks mentioned above with prior art processes, comprises the steps of:
(a) providing a semiconductor structure including at least a gate oxide layer formed on a surface of a semiconductor substrate, said structure being divided into array regions and support regions which may have different oxide thicknesses;
(b) forming a gate stack on said structure, said gate stack including a layer of polysilicon formed on the gate oxide layer, a conductor material layer formed on said layer of polysilicon, and a nitride cap layer formed on said conductor material layer;
(c) partially mask open etching the gate stack by patterning the nitride cap layer and etching through the gate stack stopping on said layer of polysilicon;
(d) forming spacers on exposed sidewalls of said partially etched gate stack;
(e) completing said mask open etching in said array regions by removing any exposed polysilicon, while not etching said layer of polysilicon in the support regions;
(f) performing a first oxidation step on the structure so as to form an oxide layer on exposed polysilicon sidewalls in said array regions while simultaneously forming a sacrificial oxide layer on said layer of polysilicon in said support regions;
(g) selectively removing said spacers in said support regions of said structure;
(h) selectively removing said sacrificial oxide layer and said layer of polysilicon in said support regions; and
(i) performing a second oxidization step on said structure so as to form an array oxide layer and a support oxide layer, said array oxide layer having a thickness that is greater than the support oxide layer, said array oxide layer comprising oxide layers from said first and second oxidation steps.
In one embodiment of the present invention, a barrier layer is formed between the layer of polysilicon and conductor material layer. When a barrier layer is present, it may be optionally removed during one of the above mentioned etching steps, i.e., steps (c) or (e).
In accordance with another aspect of the present invention, a memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the inventive structure of the present invention comprises:
a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions,
said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, and
said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-7
are cross-sectional views depicting a semiconductor memory structure through the various processing steps of the present invention.


REFERENCES:
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patent: 5783458 (1998-07-01), Kadosh et al.
patent: 5858848 (1999-01-01), Gardner et al.
patent: 5863824 (1999-01-01), Gardner et al.
patent: 5882973 (1999-03-01), Gardner et al.
patent: 5905293 (1999-05-01), Jeng et al.
patent: 590962

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