Gate pattern formation using a BARC as a hardmask

Details Gate pattern formation using a BARC as a hardmask Gate pattern formation using a BARC as a hardmask

1997-09-05

2000-09-19

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438952, 438717, 438736, H01L 213205, H01L 214763

Patent

active

061211230

ABSTRACT:
A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.

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