Gate modeling for semiconductor fabrication process effects

Details Gate modeling for semiconductor fabrication process effects Gate modeling for semiconductor fabrication process effects

2007-02-16

2009-08-18

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

07577932

ABSTRACT:
In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.

REFERENCES:
patent: 5610833 (1997-03-01), Chang et al.
patent: 6219630 (2001-04-01), Yonezawa et al.
patent: 6562638 (2003-05-01), Balaskinski et al.
patent: 2005/0132306 (2005-06-01), Smith et al.
patent: 2005/0251771 (2005-11-01), Robles

Affiliated with

Also associated with

Rating

Gate modeling for semiconductor fabrication process effects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate modeling for semiconductor fabrication process effects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate modeling for semiconductor fabrication process effects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4110961