Gate insulator process for nanometer MOSFETS

Details Gate insulator process for nanometer MOSFETS Gate insulator process for nanometer MOSFETS

1999-04-07

2002-07-02

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S294000, C438S296000

Reexamination Certificate

active

06413826

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of semiconductor devices, particularly devices having a nitrided silicon substrate manufactured by nitrogen ion implantation and having high dielectric constant insulators.
2. Description of Related Art
As semiconductor devices are made smaller to accommodate desired increases in device density, it is desirable to decrease the dimensions of the insulating elements in the devices. Particularly, the minimum dimensions of metal on silicon field effect transistors (“MOSFETS”) in semiconductors can be limited by the requirements for effective insulation, or “gate insulation” between the silicon substrate and gates. For example, in non-volatile memory devices, the gate insulator prevents charge leakage from occurring between the gate and the substrate. Typically, an insulator such as SiO
2
is used to provide the gate, and is called “gate oxide.” However, the minimum thickness of the insulating layers can be determined in part by the dielectric constant of the insulating material. Therefore, as semiconductor device density increases and device dimensions become smaller, it becomes increasingly useful to provide insulating materials that have high insulating capability. Recently, materials having high insulating capability and high capacitance have become available, and have been used to provide alternatives to SiO
2
as gate insulators.
A. Semiconductor Device Manufacture
The manufacture of semiconductor devices is typically carried out by creating areas of isolation or insulation on a semiconductor substrate, such as silicon, and then forming active devices between the areas of electrical isolation. The semiconductor substrate can typically be a p-doped substrate, although one can alternatively use an n-doped substrate. Insolation areas can be manufactured, by way of example, using Shallow Trench Isolation (“STI”), whereby areas of electrical isolation are formed by inscribing trenches in the silicon substrate and then filling the trenches with an insulating material, including, by way of example only, a silicon oxide. The prior art methods of manufacturing devices using STI are depicted in
FIGS. 1-3
.
FIG. 1
depicts a semiconductor wafer
100
comprised of a silicon substrate
104
and having a layer of pad oxide (“Pox”)
108
formed thereon. The pad oxide can be formed by way of example, by dry oxidation of silicon in the presence of oxygen (O
2
) at a temperature of about 950° C. for about 30 minutes.
FIG. 2
depicts the semiconductor wafer shown in
FIG. 1
, but after the layer of pad oxide
108
is formed, a photoresist mask (not shown) is applied to the substrate and a layer of nitride
112
is deposited over the wafer, leaving those areas uncovered where shallow trenches are to be formed.
FIG. 3
depicts the same semiconductor wafer as in
FIG. 1 and 2
, but after a shallow trench
116
has been formed in the substrate between the areas having the nitride layers
112
. The nitride layer
112
can act as an etch-stop layer to prevent the removal of substrate
104
during the formation of shallow trenches, thus providing for localized areas of electrical isolation. Subsequently, the shallow trenches are filled with a dielectric material such as silicon dioxide, and thereafter the nitride layer
112
is removed, thereby exposing the layer of pad oxide
108
.
The next step in semiconductor device manufacture is typically the deposition of a layer of insulating material or gate insulator on the pad oxide. Gate insulating layers are typically made of SiO
2
and after formation of a gate insulator, the manufacture of semiconductor devices involves the deposition of a conductive material on top of the insulating material, thereby forming a “gate” structure which forms part of the active device elements. Because the dielectric constant of SiO
2
is about 3.9, and other materials can have dielectric constants higher than that of SiO
2
, it can be desirable to incorporate other, high-dielectric constant materials into gate insulators.
B. High-Dielectric Constant Insulators
One indicator of a material's ability to act as an electrical insulator is the dielectric constant (“K”). The dielectric constant is a measure of the ability of an insulator to prevent the discharge of electric current between conductive elements through the insulator. Better insulators have higher dielectric constants. The dielectric constant is quantified by comparing the insulating ability of an insulating material to the insulating ability of air, which has a dielectric constant defined to be 1.0. The commonly used dielectric material, silicon dioxide (SiO
2
) has a dielectric constant of about 3.9. High dielectric constant materials are herein defined to have dielectric constants of greater than 3.9. In contrast, insulators having dielectric constants of less than 3.9 are herein considered to be low dielectric constant insulators.
Examples of high dielectric constant materials include tantalum pentoxide (Ta
2
O
5
), aluminum oxide (Al
2
O
3
), silicon nitride (Si
3
N
4
), zirconium dioxide (ZrO
2
), titanium dioxide (TiO
2
), barium-strontium-titanium oxide (“BST”), and lead-zirconium-titanium oxide (“PZT”), although other materials can also be used. Tantalum pentoxide has a dielectric constant of about 30, and therefore, is a useful material because it can be made into an insulating layer having high capacitance. Other materials, having dielectric constants up to about 200 are known in the art, and can be desirably used as gate insulators.
High-dielectric constant materials are desired for use as insulators because of the possibility that the increased dielectric constant and capacitance can permit the use of thinner layers of insulating materials, permitting device dimensions to be smaller than previously possible using more conventional insulators. Therefore, to take advantage of high-dielectric constant materials, instead of depositing SiO
2
as the gate oxide, more recent manufacturing methods have incorporated high dielectric constant materials. Unfortunately, conventional manufacturing methods involving high dielectric constant insulators can suffer from the problem of interfacial oxide formation between the silicon substrate and the high dielectric material.
C. Sacrificial Oxide and Interfacial Oxide Layers
Silicon wafers, as depicted in
FIG. 1
, typically can have a thin layer of oxide
108
on the surface. This layer of oxide can be termed “sacrificial oxide” or “pad oxide.” As depicted in
FIG. 4
, with the deposition of the high dielectric constant material
132
, a layer of silicon oxide
110
(“interfacial oxide”) can form under the high dielectric constant material. The interfacial oxide can have the structural formula Si
X
O
y
, where x and y are not necessarily integers. Although the interfacial oxide can be thin, it can provide an oxide equivalent thickness of about 10 Å. Oxide equivalent thickness (“Ox
eq
”) of an insulating layer X, is defined as the thickness of a layer of SiO
2
sufficient to provide the same accumulation capacitance as the insulating layer X. Ox
eq
can be calculated from the thickness of the insulating layer, T, and dielectric constant of the insulator, K, according to the formula:
Ox
eq
=
T
⨯
3.9
K
.
However, like conventional gate oxide, interfacial oxide has a dielectric constant of about 3.9. Thus, the conductive layer of the gate structure is separated from the silicon substrate by the layer of high dielectric constant material and the interfacial oxide which underlies the high dielectric constant layer.
Nevertheless, as device dimensions are reduced, and as the thickness of the high dielectric constant layer is reduced, the capacitance of the insulator should remain at a high, desirable level. Unfortunately, the formation of a layer of interfacial oxide during deposition of the high-dielectric constant material can result in the formation of a mixed insulating layer. This mixed layer can have a capacitance less than that of the high dielectric con

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