Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2001-11-06
2003-04-29
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S786000
Reexamination Certificate
active
06555483
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a gate insulation film having a slanted nitrogen concentration profile and, more particularly, to a MOSFET having a gate insulation film which prevents degradation of the on-current characteristic of the MOSFET.
(b) Description of the Related Art
LSIs (large-scale integrated circuits) are categorized into two types including a memory device and a logic device. Both types of LSIs are generally implemented by MOSFET circuits by taking advantages of higher integration capability and low costs thereof.
As is well known, the operational principle of the MOSFET is such that a control voltage applied to the gate electrode, which is disposed on the semiconductor substrate with an intervention of a gate insulation film therebetween, controls the conductivity of the channel region induced on the surface area of the semiconductor substrate just under the gate insulation film. In this respect, the gate insulation film is the key element of the semiconductor device comprised of the MOSFET circuits, and it is one of the most important issues to form the gate insulation film with higher reliability and superior controllability.
In the recent logic devices, under the circumstances as described above, a silicon oxide (SiO
2
) film widely used as the gate insulation film has a thickness as low as about 3.0 nanometers (nm), and this thickness becomes further smaller responding to the requirement of higher performances of the logic devices.
The smaller thickness of the gate insulation film involves the problems of increase in the gate leakage current and penetration of impurities through the gate insulation film from the gate electrode. The former results from the degradation of the insulation capability of the gate insulation film due to the smaller thickness. On the other hand, the latter occurs when impurity ions such as boron or phosphorous ions doped in the gate electrode made of polysilicon, for example, readily penetrate the thin gate insulation film during the heat treatment in the fabrication process.
In particular, the latter causes a change or variance in the conductivity of the channel due to the impurity ions reached to the channel by the penetration, whereby the characteristics of the MOSFET such as the drain current and the threshold voltage thereof significantly vary to affect the operation of the MOSFET.
In order to suppress the increase in the gate leakage current, it is effective to use another insulation film having a higher dielectric constant as the gate insulation film instead of the silicon oxide film, as known in the prior art. In order to suppress the impurity penetration, it is effective to dope the silicon oxide film with nitrogen to form a silicon oxynitride (SiON) film. It is known that the silicon oxynitride film has a higher dielectric constant compared to the silicon oxide film. Thus, the silicon oxynitride film has been used in the prior art for suppression of the increase in the gate leakage current and the impurity penetration through the gate insulation film.
Patent Publication JP-A-6(1994)-140392, for example, describes a fabrication process for a semiconductor device, wherein a silicon oxynitride film formed by nitriding a silicon oxide film is used as the gate insulation film. In the described process, nitrogen radicals generated by optical excitation alone or in combination with plasma excitation are used for nitriding the silicon oxide film. In the nitriding step, the optical excitation process provides an energy assistance for the nitriding, whereby even a relatively lower temperature between 700 and 900 degrees C effects the nitriding.
There is a problem in the process as described above that the nitrogen radicals are generated by using the optical excitation, which is generally difficult to control. In addition, an optimum temperature profile with time for the process of introducing the nitrogen radicals into the silicon oxide film is not described therein and is difficult to find. Thus, it is desired to form a silicon oxynitride film with a suitable reproducibility and in-plane uniformity in the fabrication of MOSFETs in a semiconductor device.
FIG. 1
is a sectional view of a typical semiconductor device which may be fabricated by the process described in the above publication, and
FIG. 2
is an enlarged partial view thereof.
The semiconductor device includes a p-type silicon substrate
12
, an isolation region
13
formed by a STI technique on the silicon substrate
12
, a p-well formed in the active region isolated by the isolation region
13
, a threshold-controlling well
15
formed in the surface area of the p-well
14
, an n-type source region
16
including a lightly doped region
16
A and a heavily doped region
16
B selectively formed in the threshold-controlling well
15
, an n-type drain region
17
including a lightly doped region
17
A and a heavily doped region
17
B selectively formed in the threshold-controlling well
15
, a gate electrode
19
formed on the silicon substrate
12
with an intervention of a gate insulation film
18
therebetween, side-wall insulation films
20
covering the side walls of the gate insulation film
18
and the gate electrode
19
, a pair of source/drain electrodes
21
and
22
formed on the n-type source/drain regions
16
and
17
, respectively.
In
FIGS. 1 and 2
, an nMOSFET is exemplified, wherein the n-type source/drain regions
16
and
17
have a so-called LDD (lightly doped drain) structure.
The gate insulation film
18
has a two-layer structure including a silicon oxide film
23
and an overlying silicon oxynitride film
24
, as shown in FIG.
2
. The overall thickness of the gate insulation film
18
is around 1.75 nm. In fact, the thickness of the silicon oxide film
23
is around 1.6 nm before the silicon oxynitride film
24
is formed by nitriding the silicon oxide film.
FIGS. 3A
to
3
E show consecutive fabrication steps of a conventional fabrication process for the nMOSFET of FIG.
1
. An isolation region
13
, a p-well
14
and a threshold-controlling well
15
are first formed on a p-type silicon substrate
12
, followed by heat treating the same in a chamber of a single-wafer-processing type, for example. Thus, a silicon oxide film
23
having a thickness of about 1.6 nm is formed on the substrate
12
, as shown in FIG.
3
A.
Subsequently, nitrogen is introduced into the silicon oxide film
23
to form a silicon oxynitride film
24
on top of the silicon oxide film
23
, as shown in FIG.
3
B. In this step, the silicon wafer is received in a plasma chamber, after plasma is generated by applying a power source to nitrogen gas to change the same into plasma source including nitrogen atoms and nitrogen radicals. The silicon wafer is heated based on the typical temperature profile having a rising slope
70
A having a rising rate of 75 degrees C. per second, a flat peak
70
B at 950 degrees C., and a falling slope
70
C having a rising rate of 40 degrees C. per second, as shown in FIG.
4
.
The power source is turned OFF at the last of the flat peak
70
B of the temperature profile. By using the plasma source together with the heat treatment, nitrogen is introduced to the surface area of the silicon oxide film
23
to from a silicon oxynitride film
24
on the silicon oxide film
23
. This process is called a rapid thermal process (RTP). The original thickness of the gate insulation film
18
at 1.6 nm is changed to 1.75 nm after the RTP.
Subsequently, a polysilicon (polycrystalline silicon) film
25
is deposited using a CVD technique on the entire surface of the wafer, as shown in
FIG. 3C
, followed by patterning the polysilicon film
25
and the silicon oxide film
23
together with the silicon oxynitride film
24
by using a known photolithographic technique, to thereby form a gate insulation film
18
and a gate electrode
19
, as shown in FIG.
3
D.
Thereafter, n-type impurities are introduced by an ion-implantation technique using the gate electrode
19
as a mask to form a lightly doped regio
Chaudhuri Olik
NEC Corporation
Pham Thanh V
Scully Scott Murphy & Presser
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