Gate etch process

Details Gate etch process Gate etch process

2002-03-15

2004-03-02

Eckert, George (Department: 2815)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C156S922000, C156S922000, C438S072000, C438S494000, C438S636000, C438S689000, C438S691000, C438S695000, C438S712000, C438S713000, C438S717000, C438S719000, C438S720000, C438S724000, C438S734000, C438S738000, C438S749000, C438S757000, C438S952000

Reexamination Certificate

active

06699795

ABSTRACT:

BACKGROUND
Modern integrated circuits are constructed with up to several million active devices, such as transistors and capacitors, formed in a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polysilicon and metal, which are etched to form conductors for carrying signals between the various active devices. The conductive layers and interlayer dielectric are deposited on the silicon substrate wafer in succession, with each layer being, for example, of the order of 1 micron in thickness.
A common intermediate structure for constructing integrated circuits is the stack shown diagrammatically in FIG.
1
. This structure has a gate oxide (GOX,
10
), which supports a layer of polycrystalline silicon (polysilicon,
12
).
Above the polysilicon layer is a layer of silicon nitride (
14
), followed by a layer of an anti-reflective coating (ARC,
16
). Finally, a resist material
18
is present on top of the structure. The resist layer is patterned, followed by etching of the structure in the regions not covered by the resist material, allowing for the formation of functional elements within the structure, such as gates.
The conventional etching process for a structure such as the stack is illustrated in the diagram of FIG.
2
. In this illustration, the etching steps are represented as patterned boxes, and an individual step etches the layer shown to the left of the etch box. Overetch steps are indicated by the fact that the lower limit of the etch box is positioned below the lower limit of the layer box. The step of etching the ARC,
20
, is performed at medium pressure; and an overetch step, as indicated by the lower boundary of the etch positioned below the lower boundary of the ARC
16
, is employed to insure the complete removal of the ARC. This etch is followed by a nitride etch step
22
, using a low ratio of CF
4
to CHF
3
, to overetch the silicon nitride layer
14
. Finally, a main etch step
24
of the polysilicon
12
followed an overetch step
26
removes all material except the GOX base
10
.
During this etching, defects can be formed which span the entire height of the stack, i.e. from the GOX base to the resist layer. These cylindrical defects, having a diameter from 50-80 nanometers (nm), are known as “drips.” The number of drips in a typical structure is from 50-100 drips per square centimeter (drips/cm
2
). These defects cause contact open and single bit failure, resulting in structures which are not useful. Efforts to minimize the number of drips have come at the expense of critical dimension (CD) control, meaning that the size of the desired structural element formed is too large. There is thus a need for an etching process which can reduce the number of drips while maintaining acceptable CD control.
BRIEF SUMMARY
In a first aspect, the present invention is a method of making a semiconductor structure, comprising etching an anti-reflective coating layer with an ARC etch plasma at a pressure of at most 10 millitorr; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.
In a second aspect, the present invention is a method of making a semiconductor structure, comprising etching an anti-reflective coating layer at a pressure of at most 6 millitorr; overetching the anti-reflective coating layer; etching a nitride layer with a first nitride etch plasma having a F:C ratio of at least 3.8; etching the nitride layer with a second nitride etch plasma having a F:C ratio at most 3.7; and overetching the nitride layer with the second nitride etch plasma. The semiconductor structure has at most 1 drip per square centimeter and has a minimum feature size of at most 1.8 micrometers.
In a third aspect, the present invention is a semiconductor structure, comprising a gate oxide; a polysilicon layer on the gate oxide; a silicon nitride layer on the polysilicon layer; and an anti-reflective coating layer on the polysilicon layer. The semiconductor structure has a minimum feature size of at most 1.8 micrometers and has at most 10 drips per square centimeter.
In a fourth aspect, the present invention is, in a method of making a semiconductor structure including etching an anti-reflective coating layer with an ARC etch plasma, etching a nitride layer, and etching a polysilicon layer; the improvement comprising applying the ARC etch plasma at a pressure of at most 10 millitorr; and etching the nitride layer with a first nitride etch plasma having a first F:C ratio, followed by a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.


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Wolf, “Silicon Processing for the VLSI Era”, vol. 1-Process Technology, pp. 550-556.

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