Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-05-15
2011-10-04
Lee, Calvin (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S317000
Reexamination Certificate
active
08030161
ABSTRACT:
A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
REFERENCES:
patent: 5557123 (1996-09-01), Ohta
patent: 5768192 (1998-06-01), Eitan
patent: 5973353 (1999-10-01), Yang et al.
patent: 6091120 (2000-07-01), Yeom et al.
patent: 6313498 (2001-11-01), Chen
patent: 6664604 (2003-12-01), Besser et al.
patent: 6885586 (2005-04-01), Chen et al.
patent: 2006/0105525 (2006-05-01), Kim et al.
patent: 2006/0118858 (2006-06-01), Jeon et al.
patent: 2006/0163656 (2006-07-01), Rim
patent: 2006/0198216 (2006-09-01), Park et al.
patent: 2007/0045715 (2007-03-01), Sudo et al.
patent: 2007/0108498 (2007-05-01), Lee et al.
Clementi, C.; Bez, R.; Olivetti, V.C. “Non Volatile Memory Technologies: Floating Gate Concept Evolution,”Mater. Res. Soc. Symp. Proc., 2005, 830, pp. D1.2.1-D1.2.12.
Dimitrakis, P.; Normand, P. “Semiconductor Nanocrystal Floating-gate Memory Devices,”Mater. Res. Soc. Symp. Proc., 2005, 830, pp. D5.1.1-D1.5.14.
Fazio, A. “Flash Memory Scaling,”MRS Bulletin, 2004, 29(11), pp. 814-817.
Goronkin, H.; Yang. Y. “High-Performance Emerging Solid-State Memory Technologies,”MRS Bulletin, 2004, 29(11), pp. 805-813.
Jeong, H.; Kim, K. “Prospect of Emerging Nonvolatile Memories,”Mater. Res. Soc. Symp. Proc., 2005, 830, pp. D7.6.1-D7.6.9.
Nafis, S.; Owyang, J.; Chatterji, S. “The Thin-film Landscape for ALD Processing,”Solid State Technology, 2006, 49(5), 8 pages.
Power, J.R.; Gong, Y.; Tempel, G.; Andersen, E.O.; Langheinrich, W.: Shum, D.; Strenz, R. “Improved Reliability of a High-k IPD Flash Cell Through Use of a Top-oxide,”2007 22ndIEEE Non-Volatile Semiconductor Memory Workshop, IEEE, Piscataway, New Jersey, USA, 2007, pp. 27-29.
Prall, K. “Scaling Non-Volatile Memory Below 30nm,”2007 22ndIEEE Non-Volatile Semiconductor Memory Workshop, IEEE Piscataway, New Jersey, USA, 2007, pp. 5-10.
Silva, H.; Kim, M.K.; Avci, U.; Kumar, A.; Tiwari, S. “Nonvolatile Silicon Memory at the Nanoscale,”MRS Bulletin, 2004, 29(11), pp. 845-851.
Van Houdt, J.; Wouters, D. “Memory Technology: Where is it Going?” Semiconductor International, Dec. 1, 2006, 6 pages.
Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, California, USA, 2002, pp. 145-147.
Chen Jian
Duan Xiangfeng
Leon Francisco A.
Parce J. Wallace
Brinks Hofer Gilson & Lione
Lee Calvin
Nanosys Inc.
LandOfFree
Gate electrode for a nonvolatile memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate electrode for a nonvolatile memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate electrode for a nonvolatile memory cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4282374