Gate electrode doping method for forming semiconductor...

Details Gate electrode doping method for forming semiconductor... Gate electrode doping method for forming semiconductor...

2002-06-04

2004-12-28

Guerrero, Maria F. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000, C438S197000, C438S585000

Reexamination Certificate

active

06835622

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming gate dielectric layers within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for forming multiple gate dielectric layers with multiple thicknesses within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates over which are formed patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor integrated circuit microelectronic fabrication functionality levels have increased, it has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses. Within the context of the present invention, gate dielectric layers are intended as dielectric layers which are formed directly upon semiconductor substrates, whether or not they are employed within field effect transistor (FET) devices, although gate dielectric layers are most typically employed within field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications. Similarly, although gate dielectric layers within semiconductor integrated circuit microelectronic fabrications are most commonly formed employing thermal oxidation methods, gate dielectric layers within semiconductor integrated circuit microelectronic fabrications may also be formed employing various combinations of thermal oxidation methods, deposition methods and nitridation methods.
It has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses insofar as the functional requirements and operational requirements of the pluralities of semiconductor devices formed within the semiconductor integrated circuit microelectronic fabrications often demand the plurality of gate dielectric layers having the plurality of gate dielectric layer thicknesses. For example and without limitation, within embedded semiconductor integrated circuit microelectronic fabrications (i.e., semiconductor integrated circuit microelectronic fabrications which perform both a logic function and a memory function), it is common to employ comparatively thin gate dielectric layers within field effect transistor (FET) devices which perform the logic function, such as to enhance operating speed of the field effect transistor (FET) devices which perform the logic function, while employing comparatively thick gate dielectric layers within field effect transistor (FET) devices which perform memory functions or other peripheral functions, wherein the field effect transistor (FET) devices which perform the memory function or other peripheral function may be subject to comparatively higher operating voltages.
While it is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, and often unavoidable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, forming within semiconductor integrated circuit microelectronic fabrications such semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses is not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses with enhanced manufacturability and reliability of the semiconductor integrated circuit microelectronic fabrications.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, with enhanced manufacturability and reliability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses, pluralities of semiconductor devices within semiconductor integrated circuit microelectronic fabrications.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Barsan et al., in U.S. Pat. No. 5,672,521 (a method which employs implanting into a first region of a silicon semiconductor substrate a dose of a dopant which enhances thermal oxidation of the silicon semiconductor substrate and implanting into a second region of the silicon semiconductor substrate a dose of a nitrogen dopant which inhibits thermal oxidation of the silicon semiconductor substrate, such that upon thermal oxidation of the silicon semiconductor substrate including the first region, the second region and an unimplanted third region there is formed upon the silicon semiconductor substrate a gate dielectric layer having three thickness regions); (2) Chwa et al., in U.S. Pat. No. 6,147,008 (a method which employs implanting through a gate dielectric layer formed upon a silicon semiconductor substrate a dose of a nitrogen implanting ion which inhibits thermal oxidation of the silicon semiconductor substrate and then patterning the gate dielectric layer to form a patterned gate dielectric layer which leaves exposed implanted and unimplanted portions of the silicon semiconductor substrate, prior to thermally oxidizing the silicon semiconductor substrate to reform a gate dielectric layer having three thickness regions); (3) Song, in U.S. Pat. No. 6,191,049 (an additional ion implanting method which employs nitrogen implanting ions and fluorine implanting ions to assist in providing a semiconductor substrate which upon thermal oxidation may have formed thereupon a gate dielectric layer with three thickness regions); (4) Balasubramanian et al., in U.S. Pat. No. 6,235,591 (a sequential thermal annealing method for forming differential gate oxide layer thicknesses within semiconductor integrated circuit microelectronic fabrications with enhanced reliability by employing a bilayer sacrificial mask layer formed of other than a photoresist material); and (5) Huang, in U.S. Pat. No. 6,265,267 (an integrated method for fabricating a flash memory semiconductor integrated circuit microelectronic fabrication having multiple gate dielectric layer thicknesses while employing a polysilicon layer as an oxidizable and sacrificial layer with respect to an intergate dielectric layer within a split gate field effect transistor (FET) device within the flash

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