Gate dielectric first replacement gate processes and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S197000, C438S201000, C438S203000, C438S207000, C438S216000, C257SE21444, C257SE21637

Reexamination Certificate

active

07838356

ABSTRACT:
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

REFERENCES:
patent: 6124165 (2000-09-01), Lien
patent: 7208361 (2007-04-01), Shah et al.
patent: 2006/0022277 (2006-02-01), Kavalieros et al.
patent: 2006/0091483 (2006-05-01), Doczy et al.
patent: 2007/0042583 (2007-02-01), Jang et al.

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