Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-24
2001-10-09
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S253000
Reexamination Certificate
active
06300179
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic devices, and more particularly to a gate device with an access channel formed in a discrete post and to a method for fabricating the same.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers and other integrated circuits. One type of memory array is a dynamic random access memory (DRAM) in which memory cells retain information only temporarily and are refreshed at periodic intervals. Despite this limitation, DRAMs are widely used because they provide low cost per bit of memory, high device density, and feasibility of use.
DRAMs typically include an array of memory cells accessed by a series of word lines and bit lines. Each memory cell includes an access transistor coupled to a storage capacitor. The access transistor is formed from a portion of a word line disposed over a channel that is defined in an underlying substrate. A source and drain for the access transistor are also defined in the substrate. The source is shared with an adjacent access transistor and connected to a bit line. The drain is connected to the storage node.
Efforts to increase DRAM density have concentrated on minimizing the planar area of the memory cells. The planar area of the cells, however, is constrained by the configuration of the access transistor, the storage node, the word line, and the bit line.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved gate device and method are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides a high density gate device for a memory array or other integrated circuit.
In one embodiment of the present invention, a method for fabricating a gate device includes forming a discrete post on a substrate. The discrete post protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the discrete post. A gate structure is formed and operable to control the access channel to selectively couple the first terminal to the second terminal.
More specifically, in accordance with one embodiment of the present invention, the gate device is used in a memory cell. In this embodiment, a storage node is coupled to the first terminal and a bit line is coupled to the second terminal. The gate structure is operable to control the access channel to selectively couple the bit line to the storage node.
Technical advantages of the present invention include providing a very high density gate device for memory arrays and other integrated circuits. In particular, the gate device has a raised channel formed in a discrete post with individual source and drain terminals for the channel. The terminals may be formed in or adjacent to the discrete posts. In either case, the use of individual source and drain terminals allows the gate device to be scaled down to minimal isolation between devices.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.
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Brady III W. James
Chaudhuri Olik
Pham Hoai
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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