Gate coupling in floating-gate memory cells

Details Gate coupling in floating-gate memory cells Gate coupling in floating-gate memory cells

2006-10-03

2006-10-03

Fourson, George R. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S264000, C438S265000, C438S266000, C438S267000, C257SE29129, C257SE21179

Reexamination Certificate

active

07115458

ABSTRACT:
Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.

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