Gate-contact structure and method for forming the same

Details Gate-contact structure and method for forming the same Gate-contact structure and method for forming the same

2005-02-15

2005-02-15

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S368000

Reexamination Certificate

active

06855978

ABSTRACT:
A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

REFERENCES:
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5650648 (1997-07-01), Kapoor
patent: 6057193 (2000-05-01), Wang et al.
patent: 6417539 (2002-07-01), Gardner et al.
patent: 6501122 (2002-12-01), Chan et al.
patent: 6524868 (2003-02-01), Choi et al.

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