Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-28
2003-05-13
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S216000, C438S261000, C257S310000
Reexamination Certificate
active
06563183
ABSTRACT:
TECHNICAL FIELD
The present invention relates to methods for fabricating an array of field effect transistors on a semiconductor substrate, and more particularly for fabricating an array wherein each gate has a the gate dielectric with dielectric properties independent of other gates in the array.
BACKGROUND OF THE INVENTION
Integrated circuits typically utilize an array of field effect transistors, each of which comprises a polysilicon gate positioned over a channel region within a silicon substrate. An insulating layer, typically called a gate oxide, separates the polysilicon gate from the channel region.
The typical process for fabricating a polysilicon gate is to first grow an oxide on the surface of a substrate followed by applying a polysilicon layer. An anti-reflective coating and a photoresist layer are then deposited over the polysilicon layer, patterned, and-developed to mask the polysilicon gate. An anisotropic etch is then used to remove the un-masked polysilicon such that the polysilicon gate is formed.
It is a generally recognized goal to decrease the size of the polysilicon gate. Decreasing the gate size permits decreasing the size of each individual silicon device. Decreasing the size of each device provides the ability to increase the density of the transistor array fabricated on the substrate which provides the ability to fabricate a more complex circuit on a substrate of a given size. Additionally, a smaller channel region beneath a smaller gate reduces capacitance across the channel/source junction and the channel drain junction which provides for faster operating speed and reduced power consumption.
Reducing the gate size requires reducing the thickness of the gate oxide to maintain adequate capacitive coupling between the gate and the channel region. Further, there exists a minimum physical thickness of the gate oxide at which the oxide no longer isolates the gate from the channel region. Therefore, there exists a minimum gate size that can be achieved when silicon dioxide is used as the gate oxide. Therefore, it has been proposed to use other dielectrics with dielectric constants greater than the dielectric constant of silicon dioxide (e.g high K dielectrics) in the dielectric layer to replace silicon dioxide such that capacitive coupling is improved (e.g. smaller electrical thickness) while a larger physical thickness is maintained. With the use of high K dielectrics, very small transistor structures and dense transistor arrays can be fabricated. It is envisioned that such complex circuits will require the use of transistors with different operating properties.
Accordingly there is a strong need in the art for an integrated circuit with an array of transistors wherein each transistor may be fabricated with a gate dielectric that includes dielectric properties independent of dielectric properties of adjacent transistors.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor.
The first field effect transistor comprises a first polysilicon gate positioned above a first channel region of the substrate and isolated from the first channel region by a first dielectric layer extending the entire length of the first polysilicon gate. The first dielectric layer comprises a first dielectric material with a first dielectric constant.
The second field effect transistor comprises a second polysilicon gate positioned above a second channel region on the substrate and isolated from the second channel region by a second dielectric layer extending the entire length of the second polysilicon gate. The second dielectric layer comprises a second dielectric material with a second dielectric constant. The first dielectric constant and the second dielectric constant may be different and both may be greater than the dielectric constant of silicon dioxide.
In one embodiment, the second dielectric layer may itself comprise multiple layers. As such, the second dielectric layer may comprise a third dielectric layer adjacent to the second dielectric layer (and adjacent to either the second polysilicon gate or adjacent to the substrate) extending the entire length of the second polysilicon gate. The third dielectric layer may comprise a third dielectric material which may, or may not, be the same as the first dielectric material.
The thickness of the first dielectric layer and the second dielectric layer (as measured between the substrate and the polysilicon gate) may or may not be the same. Further, the thickness of the first polysilicon gate and the second polysilicon gate may or may not be the same.
A second aspect of the present invention is to provide a method of fabricating an integrated circuit on a semiconductor substrate. The method comprises: a) depositing a first high K dielectric on the substrate; b) fabricating a mask on the surface of the first high K dielectric to mask a first portion and to expose a second portion; c) removing the first high K dielectric to expose the substrate in the second portion; d) depositing a second high K dielectric on the substrate in the second portion; e) depositing a polysilicon layer over the first portion and the second portion; f) fabricating a mask on the surface of the polysilicon layer to mask a first gate in the first portion and to mask a second gate in the second portion; and g) etching the polysilicon layer, the first high K dielectric and the second high K dielectric to form the first gate and the second gate.
The step of depositing the second high K dielectric on the substrate in the second portion may comprise depositing the second high K dielectric over the entire surface including the substrate in the second portion and at least one of the mask and the first high K dielectric in the first portion. Thereafter, the wafer may be polished to expose the first high K dielectric in the first portion.
A third aspect of the present invention is to provide an alternative method of fabricating an integrated circuit on a semiconductor substrate. The alternative method comprises: a) depositing a first high K dielectric on the substrate; b) fabricating a mask on the surface of the first high K dielectric to mask a first portion and to expose a second portion; c) altering the dielectric properties of the first high K dielectric in the second portion; d) depositing a polysilicon layer over the first portion and the second portion; e) fabricating a mask on the surface of the polysilicon layer to mask a first gate in the first portion and to mask a second gate in the second portion; and f) etching the polysilicon layer, the first high K dielectric, and the second high K dielectric to form the first gate and the second gate.
The step of altering the dielectric property of the first high K dielectric may comprise implanting the first high K dielectric with at least one of N
+
, Hf
+
, Al
+
, and Zr
+
. Alternatively, the step of altering the dielectric property of the first high K dielectric may comprise subjecting the first high K dielectric to a plasma environment to modify the work function of the first high K dielectric.
A fourth aspect of the present invention is to provide yet another alternative method of fabricating an integrated circuit on a semiconductor substrate. The method comprising: a) depositing a first high K dielectric on the substrate; b) fabricating a mask on the surface of the first high K dielectric to mask a first portion and to expose a second portion; c) removing the first high K dielectric to expose the substrate in the second portion; d) altering the dielectric properties of the first high K dielectric in the second portion; e) depositing a second high K dielectric on the substrate in the second portion; f) depositing a polysilicon layer over the first portion and the second portion; g) fabricating a mask on the surface of the polysilicon layer to mask a first gate in the first portion and to mask a second gate
En William G.
Halliyal Arvind
Lin Minh-Ren
Ngo Minh Van
Tabery Cyrus E.
Advanced Micro Devices , Inc.
Le Thao X.
Ngo Ngan V.
Renner , Otto, Boisselle & Sklar, LLP
LandOfFree
Gate array with multiple dielectric properties and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate array with multiple dielectric properties and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate array with multiple dielectric properties and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3058580