Gate array cell with predefined connection patterns

Details Gate array cell with predefined connection patterns Gate array cell with predefined connection patterns

1994-08-17

1995-06-06

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Field-effect transistor

326 41, 326 45, 257206, H03K 19173

Patent

active

054225817

ABSTRACT:
A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.

REFERENCES:
patent: 4453096 (1984-06-01), Le Can
patent: 4745305 (1988-05-01), Crafts
patent: 4771327 (1988-09-01), Usui
patent: 4785199 (1988-11-01), Kolodny
patent: 5055716 (1991-10-01), El Gamel
patent: 5270587 (1993-12-01), Zagar
patent: 5289021 (1994-02-01), El Gamel

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