Gate array architecture and layout for deep space applications

Details Gate array architecture and layout for deep space applications Gate array architecture and layout for deep space applications

1993-12-10

1996-08-06

Westin, Edward P.

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

326 13, 257206, H01L 2500, H03K 1900

Patent

active

055437362

ABSTRACT:
The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.

REFERENCES:
patent: 4623911 (1986-11-01), Pryor
patent: 4633571 (1987-01-01), Kolwicz
patent: 4727266 (1988-02-01), Fujii et al.
patent: 4745084 (1988-05-01), Rowson et al.
patent: 4851892 (1989-07-01), Anderson et al.
patent: 5060046 (1991-10-01), Shintani
patent: 5175605 (1992-12-01), Pavlu et al.

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