Gate array architecture

Details Gate array architecture Gate array architecture

2001-07-24

2002-10-08

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

Field-effect transistor

C326S045000

Reexamination Certificate

active

06462583

ABSTRACT:

BACKGROUND
1. Field
The present invention is related to integrated circuit chips and, more particularly, to gate array architectures for integrated circuit chips.
2. Background Information
Gate array architectures are commonly used for many types of integrated circuit designs. In this context, the term gate array architecture refers to a repeated pattern of transistors embedded in a semiconductor substrate, such as a silicon substrate. Typically, such architectures are employed by using a “library” that comprises unique metallization patterns to create individual cells. Such gate array architectures and libraries are commonly employed in connection with computer-aided design (CAD) and ,computer-aided manufacturing (CAM) techniques. Employing a gate array architecture stands in contrast to the custom design of the layout of transistors on a semiconductor or silicon substrate, which is also accomplished using CAD/CAM techniques. Use of gate array architectures offers the advantage of quicker or shorter fabrication and through put time, lower costs, and ease in making fixes or logic changes after a chip design has already been completed. Unfortunately, gate array architectures also have a number of shortcomings that make them less attractive for some types of applications. Typically, gate arrays or gate array architectures are not as dense, have higher power consumption, and offer lower performance than custom circuits designed using alternative approaches. A need, therefore, exists for a gate array architecture that addresses these limitations.
SUMMARY
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.
Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.
Briefly, in accordance with still another embodiment of the invention, an article includes: a storage medium, the storage medium having instructions stored thereon, the instructions, when executed, resulting in the capability to design the layout of an integrated circuit chip for fabrication, the integrated circuit chip including a gate array architecture, the gate array architecture including at least one base site being three tracks wide and in four N-type transistors and four P-type transistors


REFERENCES:
patent: 5162666 (1992-11-01), Tran
patent: 5616940 (1997-04-01), Kato et al.

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