Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2000-08-24
2002-01-01
Ghyka, Alexander G. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S697000, C438S784000, C438S787000, C438S788000, C438S911000, C427S585000, C427S578000, C427S579000, C427S588000
Reexamination Certificate
active
06335288
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of integrated circuits on a substrate. More particularly, the invention relates to a method and apparatus for improving the gap-fill capability of high-density-plasma chemical-vapor-deposition techniques.
One of the primary steps in the fabrication of modem semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (“CVD”). Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma-enhanced CVD (“PECVD”) techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio-frequency (“RF”) energy to a reaction zone near the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the temperature required for such CVD processes as compared to conventional thermal CVD processes. These advantages are further exploited by high-density-plasma (“HDP”) CVD techniques, in which a dense plasma is formed at low vacuum pressures so that the plasma species are even more reactive.
Any of these CVD techniques may used to deposit conductive or insulative films during the fabrication of integrated circuits. For applications such as the deposition of insulation films as premetal or intermetal dielectric layers in an integrated circuit or for shallow trench isolation, one important physical property of the CVD film is its ability to completely fill gaps between adjacent structures without leaving voids within the gap. This property is referred to as the film's gapfill capability. Gaps that may require filling include spaces between adjacent raised structures such as transistor gates or lines and etched trenches or the like.
As semiconductor device geometries have decreased in size over the years, the ratio of the height of such gaps to their width, the so-called “aspect ratio,” has dramatically increased. Gaps having a combination of a high aspect ratio and a small width present a challenge for semiconductor manufacturers to fill completely. In short, the challenge usually is to prevent the deposited film from growing in a manner that closes off the gap before it is filled. Failure to fill the gap completely results in the formation of voids in the deposited layer, which may adversely affect device operation, for example by trapping undesirable impurities.
The semiconductor industry is thus continuously striving to develop new technologies and new film deposition chemistries to address challenges such as the gapfill issue. For example, several years ago some manufacturers switched from a silane-based chemistry for the deposition of intermetal dielectric silicon oxide layers to a TEOS-based (tetraethoxysilane) chemistry. This switch was at least in part due to the improved gapfill capability of the TEOS-based oxide layers. While a TEOS-based chemistry does indeed have improved gapfill capabilities, it too runs up against limitations when required to completely fill sufficiently high-aspect-ratio small-width gaps.
One process that the semiconductor industry has developed to improve the gapfill capability of a variety of different deposition processes, including TEOS-based silicon oxide deposition chemistries, is the use of a multistep deposition and etching process. Such a process is often referred to as a deposition/etch/deposition process or “dep/etch/dep” for short. Such dep/etch/dep processes divide the deposition of the gapfill layer into two or more steps separated by a plasma etch step. The plasma etch step etches the upper corners of the first deposited film more than the film portion deposited on the sidewall and lower portion of the gap, thereby enabling the subsequent deposition step to fill the gap without prematurely closing it off. Typically, dep/etch/dep processes use a “sputter-etch” process in which physical sputter is combined with chemical etch. Such dep/etch/dep processes can be performed using either multiple chambers (separate chambers dedicated solely to either the deposition or etch steps) or with a single chamber in an in situ process. Generally, for any given deposition chemistry, dep/etch/dep processes can be used to fill higher-aspect-ratio small-width gaps than a standard deposition step for the particular chemistry would allow.
HDP-CVD processes were not expected to share the same gapfill problems as other CVD processes. This is because argon or another sputtering agent is commonly introduced into the gaseous mixture during an HDP-CVD deposition process, and also because the application of an RF bias provides a potential that drives directional ions. The combination of deposition gases and sputtering agent result in a process that simultaneously deposits a film over the substrate and sputters the growing film. For this reason, HDP-CVD techniques are sometimes referred to as simultaneous dep/etch processes. It has been found in practice, however, that while HDP-CVD processes generally have better gapfill capabilities than similar non-HDP-CVD processes, for certain gap widths there remains a limit to the aspect ratio of gaps that can be filled. For example, dielectric gapfill with HDP-CVD has not been achieved for straight-walled gaps having a width of 0.15 &mgr;m and with an aspect ratio that exceeds 4.5; for some gaps that have tapered walls, the gapfill limit may be at a higher aspect ratio, but an upper limit nonetheless always exists. This is due in part to the fact that the sputtering component of the HDP-CVD process acts isotropically; because of the characteristic breadloafing shape of the growing film produced during deposition, anisotropic etching removal of excess material would be more advantageous.
In view of the above problems that persist with prior-art HDP-CVD gapfill deposition techniques, new and improved methods of filling gaps with a HDP-CVD process are desirable.
SUMMARY OF THE INVENTION
The disadvantages of the prior art are overcome with a method of gapfilling that implements gas-chemistry cycling within an HDP-CVD environment. The gas-chemistry cycling can be understood by considering one particular embodiment of the invention in which a series of gaps formed between a number of stepped surfaces on the substrate are filled. In this embodiment, a dielectric film is deposited on the substrate in a process chamber through a series of gas-cycling steps. First, a gaseous mixture containing a deposition gas and an inert gas source is provided to the process chamber. A high-density plasma is generated from this gaseous mixture to deposit some material on the substrate, partially filling the gaps before a void is formed. Then, the gas chemistry is cycled so that after cooling the substrate an etchant gas is flowed into the process chamber and selectively removes material at the top of the gaps without affecting the material already in the bottom of the gap. This reopens the gap so that more material can be deposited, so the gas chemistry is cycled again, providing a gaseous mixture that contains a deposition gas and an inert gas. A high-density plasma is generated from this gaseous mixture to deposit additional material in the gaps. Depending on the characteristics of the gaps, this may be sufficient to fill them; for some gaps, continued cycling of the gas chemistry with additional etch and deposition cycles may be used to fill them completely.
The mixed deposition and sputtering characters of the HDP cycles may be characterized by the ratio of deposition to sputtering, a useful parameter being the ratio of the sum of the net deposition rate and blanket sputtering rate to the blanket sputtering rate. In one embodiment of the invention, the first HDP cycle is performed with a deposition/sputter ratio between 5 and 20; preferably, this ratio is in the range of 9-15. The depositi
Kwan Michael
Liu Eric
Applied Materials Inc.
Ghyka Alexander G.
Townsend & Townsend & Crew
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