Fusleless memory repair system and method of operation

Details Fusleless memory repair system and method of operation Fusleless memory repair system and method of operation

1997-04-07

1998-06-09

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

057645779

ABSTRACT:
A method and system for performing memory repair via redundant rows of memory uses memory elements (208 and 210) for redundant row selection instead of conventional fuses. An on-chip test controller (110) is capable of testing memory rows (106) either at wafer probe, at final testing after manufacturing, or after memory chip packaging and/or final sale to end users. If this testing identifies faulty memory rows in the memory array at any time, the electrically programmable memory elements (208 and 210) can be internally re-programmed to create a new memory configuration which includes redundant memory rows (108). This new memory configuration is enabled in order to remove the newly-detected and previously-detected faulty memory rows from active memory in the memory array.

REFERENCES:
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5430678 (1995-07-01), Tomita et al.
patent: 5535161 (1996-07-01), Kato
patent: 5544106 (1996-08-01), Koike

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