Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-12-18
2004-03-16
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S132000
Reexamination Certificate
active
06707129
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a fuse structure integrated wire bonding on the low k interconnect, and relates to methods for making the same.
2. Description of the Prior Art
It is the nature of semiconductor physics that as the feature sizes are scaled down, the performance of internal devices in integrated circuits improves in a compounded fashion. That is, the device speeds as well as the functional capability improves. The overall circuit speed, however, becomes more dependent upon the propagation speed of the signals along the interconnections that connect the various devices together. With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, it has therefore become even more important that the metal conductors that form the interconnections between devices as well as between circuits in the semiconductor have low resistivities for high signal propagation. Copper is often preferred for its low resistivities, as well as for resistance to electromigration and stress voiding properties.
On the other hand, considerable attention has focused on the replacement of silicon dioxide with new materials, having a lower dielectric constant, since both capacitive delays and power consumption depend on the dielectric constant of the insulator. Accordingly, circuit performance enhancement has been sought by combining the copper conductors with low dielectric constant layer (with dielectric constant k less than approximately 4).
Since low-k material can not sustain laser fusing, fuse of low-k interconnect is built in Al-pad layer, which is used for wire-bonding pad. As to provide good bondability for wire bonding, the Al-pad layer thickness for this pad is usually as thick as 10000 angstroms, sometimes even thicker. This is too thick for laser to blow, which diminishes the process margin of laser fusing. At some certain degree, it causes fusing failure.
For the forgoing reasons, there is a necessity for a structure for using fuse structure integrated wire bonding on the low k interconnect, and relates to methods for making the same. This invention applies a fuse open pattern in the metal layer.
SUMMARY OF THE INVENTION
In accordance with the present invention is provided to a fuse structure integrated wire bonding on the low k interconnect and relates to methods for making the same that wire bonding and process margin are provided both good bondability by laser fusing.
One object of the present invention is to provide a fuse structure integrated wire bonding on the low k interconnect and relates to methods for making the same to provide both good bondability for wire bonding and process margin for laser fusing.
In order to achieve the above objects, the present invention provides a fuse structure integrated wire bonding on the low k interconnect, and relates to methods for making the same. First of all, a first metal layer formed on the first portion of the substrate. Then, a second metal layer formed on the second portion of the substrate, wherein the second metal layer has a concavity thereon. Finally, a passivation layer on the first metal layer, the second metal layer, and the substrate, wherein the passivation layer has a first opening over the first metal layer and has a second opening substantially over the concavity of the second metal layer. The method at least includes the following steps. First of all, a cap layer is formed on the low k interconnect substrate. The low k interconnect comprises copper. Then, the metal layer is formed on the cap layer. The metal layer comprises aluminum. Next, a portion of the metal layer is removed to form a concavity of the metal layer, wherein the second opening align the hollow. The formation of Al-fuse has an extra-etch process patterned by using fuse-open mask and has been thinned down from Al-fuse thickness. The metal layer is removed to define a pad pattern and a fuse pattern on the substrate, wherein the fuse pattern have a fuse-open pattern on the top of the fuse pattern. Next, a conformal passivation layer is formed on the cap layer, the pad pattern, and the fuse pattern. The conformal passivation layer comprises silicon nitride or silicon oxide. Finally, a portion of the conformal passivation layer is removed to form a first opening on the top of the pad pattern and a second opening on the top of the fuse pattern, wherein the second opening is substantially over the concavity.
REFERENCES:
patent: 5025300 (1991-06-01), Billig et al.
patent: 5936296 (1999-08-01), Park et al.
patent: 6054340 (2000-04-01), Mitchell et al.
Clark Sheila V.
United Microelectronics Corp.
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