Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-24
2001-05-15
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S529000, C438S712000
Reexamination Certificate
active
06232210
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to fuses having application to programming of integrated circuitry, and more particularly to fuses useful for replacement of defective memory cells.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified cross-sectional view of a portion of an integrated circuit
10
. The integrated circuit
10
includes a semiconductor substrate
18
in which active circuitry, designated generally by reference numeral
20
, is fabricated. The active circuitry
20
may implement a variety of devices, including a conventional memory device, such as a dynamic random access memory (“DRAM”) or a static random access memory (“SRAM”).
Integrated circuits
10
incorporating active circuitry
20
that form a memory device include large numbers of memory cells. In fact, because of the large number of memory cells, there is a significant probability that at least some of the memory cells will be defective. Defective memory cells are typically discovered during testing and before packaging the integrated circuit
10
. To avoid the need to discard memory devices having a relatively small number of defective memory cells, techniques have been developed for the post-manufacture replacement of defective memory cells with redundant memory cells specifically provided for that purpose. Typically, memory cells are replaced in one or more groups of memory cells (i.e., rows or columns).
With further reference to
FIG. 1
, one technique for selecting defective rows or columns of memory cells for replacement is to blow a pattern of fuses to correspond to a defective row or column of memory cells. A typical fuse
25
is shown in FIG.
1
. Blowing a combination of the fuses
25
causes data to be written to or read from redundant memory cells rather than the defective memory cells corresponding to the pattern of blown fuses.
The fuses
25
are typically formed as a layer of polysilicon
24
on a dielectric layer
21
, which insulates the polysilicon layer
24
from the substrate
28
comprising the integrated circuit
10
. One or more layers of conductive material
22
, such as a layer of tungsten silicide, is then formed on the polysilicon layer
24
. For example, the conductive layer
22
may have a thickness of 1,200+/−200 angstroms and the polysilicon layer
24
may have a thickness of 1,000+/−200 angstroms. Other types of conductive material, such as metals, may be used for the conductive layer
22
or the polysilicon layer
24
. The conductive layer
22
is covered by a thin layer of dielectric material
27
that is integrally formed with a relatively thick layer dielectric layer
30
having a thickness T
1
. A first conductive layer
32
may then be fabricated on the surface of the dielectric layer
30
. The conductive layer
32
and the dielectric layer
30
may then be coated with another dielectric layer
34
having a thickness of T
2
on which a second conductive layer
36
may be fabricated. If so, the conductive layer
36
and the dielectric layer
34
may then be coated with another dielectric layer
38
having a thickness T
3
. The conductive layers
32
and
36
typically comprise polysilicon, but may be realized as metal layers.
In some applications, the fuses
25
are blown by focusing a laser beam to vaporize the layer of conductive material
22
. In these cases, the dielectric layer
27
is chosen to be transparent to the laser light, and the conductive material
22
is chosen to strongly absorb the laser light. When the laser light is incident on the conductive material
22
, the fuse
25
is blown by vaporizing the conductive material
22
. Additionally, a series of other fuses
25
may be optionally blown at this time to encode various data regarding the part being manufactured.
In other applications, the fuses
25
are blown by directing a current through selected fuses
25
that is sufficient to vaporize the layer of conductive material
22
. In either case, precise control of the thickness of the dielectric layer
27
overlying the fuse
25
is critical to successfully blowing the fuse
25
. When the dielectric layer
27
is too thick, the fuse
25
may not blow or may blow but also create a crater beneath the fuse
25
because the vaporized fusible material is confined. When the dielectric layer
27
is too thin, the fuse
25
may merely melt and then re-solidify to form a conductive stringer. Alternatively, the fuse
25
may be partially melted and partially vaporized, causing conductive, molten material to be deposited in undesirable locations. This can result in circuit malfunction.
The fuse
25
is typically exposed so that it can be blown with a laser by etching the dielectric layers
30
,
34
,
38
as shown in FIG.
1
. The etching of the dielectric layer
30
is stopped just above the fuse
25
, thereby forming the dielectric layer
27
. The etching process typically is stopped when the layer of dielectric material
27
on the fuse
25
is about 2,000 to 3,000 angstroms. When the composite thickness of the dielectric layers
30
,
34
,
38
is, for example, four microns, a 2,500 angstrom thick dielectric layer
27
is about 6.25% of the composite thickness. Thus, etching the dielectric layers
30
,
34
,
38
so that the dielectric layer
27
has a thickness in the acceptable range of 2,000-3,000 angstroms requires control of the etching process within 1.25%, i.e., 6.25%+/−1.25%. Currently used etching processes are capable of etching to 2,500+/−500 angstroms as long as the composite thickness of the dielectric layers
30
,
34
,
38
is not significantly greater than four microns. However, increasing circuit complexity requires additional conductive layers for forming interconnections and therefore additional dielectric layers formed between the conductive layers. As the composite thickness increases, it is increasingly difficult to stop the etching of the dielectric layers when the dielectric layer
27
remaining on the fuse
25
has the correct thickness. Variations in the composite thickness across the substrate
28
also increase with increases in the composite thickness of the dielectric layers, as do wafer-to-wafer variations and variations in etch rates, both across a wafer and from wafer to wafer.
There is therefore a need for a technique to provide fuses on complex integrated circuits having the correct thickness of dielectric material on the fusible material.
SUMMARY OF THE INVENTION
Briefly stated, embodiments of the present invention encompass fuses and methods of making fuses, together with systems and integrated circuits where the fuses provide benefits. The fuses are made by a method that provides control over the thickness of a dielectric layer formed on the fuse material, irrespective of the thickness of dielectric layers previously formed on the fuse. The resulting fuses maintain the electrical and mechanical characteristics needed in order to be able to blow the fuses reliably and with good fuse-to-fuse repeatability.
A fuse comprising a conductive material is formed on a substrate and a series of dielectric layers having a composite thickness are formed on the substrate and the fuse. The series of dielectric layers serves to insulate a series of conductive layers from each other. The conductive layers are formed above portions of the substrate. An opening is formed that extends through the series of dielectric layers. The opening exposes a portion of the fuse. A dielectric layer having a controlled thickness is formed on the series of dielectric layers and the fuse.
REFERENCES:
patent: 5567643 (1996-10-01), Lee et al.
patent: 5578517 (1996-11-01), Yoo et al.
patent: 5583463 (1996-12-01), Merritt
patent: 5602783 (1997-02-01), Ong
patent: 5602785 (1997-02-01), Casper
patent: 5729041 (1998-03-01), Yoo et al.
patent: 5754089 (1998-05-01), Chen et al.
patent: 5760453 (1998-06-01), Chen
patent: 5773869 (1998-06-01), Froehner
patent: 5848007 (1998-12-01), Takahashi
patent: 5879966 (1999-03-01), Lee et al.
patent: 5895962 (1999-04-01), Zheng et al.
Kauffman Ralph
Keller Dennis
Lee Roger
Deo Duy-Vu
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Utech Benjamin L.
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