Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
1997-02-24
2001-12-18
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S784000
Reexamination Certificate
active
06331739
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor integrated circuits. This invention relates particularly to integrated circuits including fuse links used to program selected features into the integrated circuit after manufacturing of the operational circuits is complete but before the integrated circuit receives its final protective coatings.
DESCRIPTION OF THE RELATED ART
The fuse links selectively program features such as redundancy in dynamic random access memory parts(DRAMs), voltage options, packaging pin out options, or any other option desired by the manufacturer to be implemented after substantial completion of the operational circuits, but before the final processing steps. This helps the manufacturer increase yield or facilitates the use of one basic design for several different end products.
The programming has often occurred by using the radiant energy of a laser beam. The laser beam is directed through a thinned section of transparent oxide material layer to heat and open a thin fuse link portion of a conductive layer carried by the semiconductor substrate. Typically the semiconductor substrate is processed to contain desired impurities and to carry desired layers of insulating material and conducting material to form the operational circuits. The operational circuits then are tested electrically and any desired options, such as using redundant circuits for non-operational circuits, are programmed into the part using a laser beam to open a certain fuse link or links.
Fuse links often have been formed as part of a conductive layer within the stack of layers formed above the semiconductor substrate. In particular, there is a thick oxide layer formed between the substrate and the fuse links. The bottom level of conductive material is patterned to form desired conductor leads and thin fuse links. The layers of conducting material formed over the bottom level of conductive material carefully avoid overlying the fuse link portions so the laser beam can access the fuse links from above. Currently as many as three layers of metal conductive material are used above the bottom layer of conductive material.
In one case, as a last step in manufacturing, the finally applied coatings of protective oxide nitride and PIX over the entire substrate are patterned and removed to provide access to the bond pads and all of the fuse links. The laser beam is directed down to a selected fuse link or links to heat and open the links. No further coatings are applied over the area opened for access to all of the fuse links. This case uses only one expensive photolithography process step to access all of the fuse links at the same time as opening the bond pads, but leaves the fuse link and the conductive materials extending from the opened fuse link exposed to the elements with no anti-moisture sealings. The exposed conductive material, such as a metal, can corrode and result in reliability problems. One solution for this is to provide a guard structure like the edge of a scribe line, but this requires larger fuse areas that increase chip size and manufacturing cost.
In another case, the oxide layers over the fuse link are patterned and etched to provide access to all of the fuse links before the protective overcoats are applied. The laser beam is then used to open the selected fuse links. The protective coatings of oxide nitride and PIX are then applied to seal the opened fuse links and photolithographically patterned to expose the bond pads. This case seals the opened fuse links from the elements, but requires the extra processing step of patterning and etching to access the fuse links in addition to patterning and etching the protective overcoats to access the bond pads. This increases manufacturing costs.
SUMMARY OF THE INVENTION
The claimed invention eliminates one photolithography step of patterning and etching in accessing the fuse links and opening the bond pads. The fuse link and bond pad are formed in the top layer of metal conducting material. The fuse link occurs at the bottom of a step in an insulating material prepared during processing and the bond pad occurs on the insulating material at a slightly higher level above the fuse link. A cap oxide then is deposited over both the fuse link and the bond pad. The cap oxide is planarized and blanket etched to expose the top surface of the bond pad while keeping the fuse link covered with a desired thickness of oxide material. This obtains an exposed bond pad and covered fuse link without an expensive processing step.
The partially completed part then can be electrically tested and any fuse programming performed through the oxide before the protective oxide nitride and PIX are applied, patterned and etched finally to expose the bond pads.
The downward step in the insulating layer that carries the fuse link can be formed by raising the bond pad section using an extra underlying layer. For example, a group of memory storage cells can be formed under the area to be used for the bond pad. Alternatively, a layer underlying the fuse link can be removed.
Alternatively, the fuse link and bond pad can be formed at the same level. In one of these cases, the cap oxide deposited over the fuse link and bond pad is removed from the bond pad by the mechanical and electrical stress of a probe needle contacting the bond pad for conducting the electrical testing. In another one of these cases, the bond pad is formed with fine slits, the cap oxide is deposited with an ECR oxide deposition technique, and the oxide etch leaves the fuse link covered while exposing the bond pad conductive material. In both of these cases, the step formation is not needed and exposing the bond pad while keeping the fuse link covered with deposited cap oxide can be achieved with only a deposition process.
REFERENCES:
patent: 4714949 (1987-12-01), Simmons et al.
patent: 4984061 (1991-01-01), Matsumoto
patent: 5404045 (1995-04-01), Mizushima
patent: 5430595 (1995-07-01), Wagner et al.
Ashigaki Shigeo
Fukuhara Hideyuki
Bassuk Lawrence J.
Brady W. James
Meier Stephen D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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