Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-23
2002-08-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S700000, C714S731000
Reexamination Certificate
active
06430720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of the functional testing of logic integrated circuits or integrated circuits including logic portions.
2. Discussion of the Related Art
The production of an integrated circuit generally includes steps of testing of the manufactured circuits. The manufacturing can itself be, possibly, aimed at a testing, when a new circuit has to be validated or the manufacturing of a circuit has to be transferred from a known technology to a new technology.
These tests are usually of two types: structural tests, on the one hand, and functional tests, on the other hand. Structural tests have the object of checking that the circuits have no physical defects which make them inoperative, these defects being independent from the applications of the circuits. Functional tests have the object of checking, for circuits exhibiting no physical defects, that these circuits operate properly for the applications for which they are meant.
These tests, generally driven by automated test machines, can be performed before encapsulation, by means of probes enabling to have access to the circuit access pads. They can also be performed after encapsulation, by having access to the circuit through its access leads.
A method to implement the functional tests is to send logic signals on the inputs (pads or leads) of the circuit to be tested, observing the states of the signals provided on its outputs (pads or leads) and comparing these states with the states theoretically expected. The states of the provided logic signals form what is usually called test patterns or vectors.
Since it is desired to continually decrease the surface of circuits while increasing the circuit integration and operating frequency, this method has several disadvantages.
First, in practice, the number of circuit inputs and outputs does not increase proportionally to the increasing complexity of the circuits. The decrease in the minimum manufacturing resolutions allows more and more complex circuits, for an equal surface, while the number of pads increases little. Indeed, this number of pads is a function of the type of package in which the circuit is to be inserted. Now, the size of the leads has to be large enough to enable a reliable welding of its leads and, proportionally, this size decreases slower than the minimum manufacturing resolutions. Since, moreover, it is generally desired to limit the surface area occupied by the circuits, this results in an increase in the number of internal circuits which are not directly accessible from the outside of the circuits. A problem of access to internal circuit elements thus arises during the tests. This is even more of a problem for circuits including, for example, internal processors using peripherals without any relation to the outside, such as program memories or dynamic memories. Internal compound testing devices made by means of shift registers disposed on the internal buses of the circuits and driven by external testing appliances may be implemented. Thereby, a better observability of the internal devices of the circuits is obtained. Indeed, a higher number of test signals can be provided, for an equal number of inputs and outputs, by using series inputs and outputs to provide the test vectors one by one and receive the states of the signals resulting from their taking into account by the circuit (these resulting states will be called resulting vectors hereafter). Conversely, this is done at the cost of the test duration since it is necessary, for each test step, to provide in series a test vector, and to receive the resulting vector. Further, a test can only be implemented step by step, which is little representative of the final operation of the tested circuit.
Another problem arises from the desire to have higher and higher performance circuits in terms of operating frequency. Indeed, for their results to be representative, the tests must be performed in normal operating conditions. This amounts, in practice, to using wide pass-band testing devices, able to provide and sample signals at the operating frequencies of these circuits, these frequencies being likely to reach several hundreds of megahertz. This sets problems of implementation of the testing devices, for example, as concerns the probes needed to access to the circuit pads or leads.
Another problem arises from the possible presence of internal circuits operating at a higher operating frequency than the internal interface circuits. Internal interface circuits are generally sized with respect to the loads that they have to withstand on the input and output pads or leads. There is a tendency to use buffer circuits, capable of providing high currents, but the performances of which are limited in terms of operating frequency, to avoid a very high power consumption. Conversely, to implement the internal logic circuits, higher frequencies may be used, the loads withstood by these circuits being generally low. If such is the case, these logic circuits will be difficult to test since, even if access can be had to these circuits via the pads or leads, the frequency will be limited by the interface circuits.
A solution to these problems is to use automated testing devices disposed in the circuits to perform functional tests, and controlled by programs disposed in the circuits.
A first problem caused by this type of solution is the surface area occupied by these internal testing resources. This surface area is occupied at the cost of the surface area occupied by the circuits actually used in the applications, which limits the useful functional surface of the circuits, and this, all the more as the tests are more complex.
The surface of these devices may be, possibly, limited by using, during tests, resources subsequently used in the applications. For example, for circuits including an internal processor, an additional memory including a test program implemented by this processor can simply be provided. A problem then is to ensure satisfactory test coverage, especially for the internal resources used to implement the test program. In the implementation of the tests, this can also cause problems in terms of control, such as the impossibility of being able to act on the tested circuit if a blocking occurs within the tested circuit.
On the other hand, such integrated devices do not offer a flexibility similar to that offered by external devices, in the implementation of the tests. For example, modifying a test program can force modification of the circuit, unless a memory accessible from the outside is available, which is not justified if this memory is used for the testing only.
SUMMARY OF THE INVENTION
An aim of the present invention is to provide an improved method of testing of integrated circuits, which overcomes the pass-band problem linked to testing devices and to internal interface circuits.
Another object of the present invention is to provide a testing method which provides a good observability of the internal operation of the tested circuits.
Another aim of the present invention is to provide a method which does not require any internal device using a significant surface area of the circuit to be tested.
Another aim of the present invention is to provide a method which offers extended possibilities in terms of testing.
Thus, the present invention provides a method of functional testing of an integrated circuit including at least one internal logic circuit to be tested, this internal logic circuit including at least one input and one output. The method includes:
providing at least one test pattern, formed of a set of logic states, on a first input of the integrated circuit, by series shifting, and storing this test pattern in a first test register, the providing step being synchronized by an external clock signal received on a second input of the integrated circuit,
serially providing this test pattern to the input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock
Frey Christophe
Hanriat Stéphane
De'cady Albert
Morris James H.
SGS-Thomson Microelectronics S.A.
Skrivanek, Jr. Robert A.
Torres Joseph D.
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