Fully silicided gate structure for FinFET devices

Details Fully silicided gate structure for FinFET devices Fully silicided gate structure for FinFET devices

2011-08-30

2011-08-30

Landau, Matthew (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S156000, C438S585000, C257SE21014, C257SE21442, C257SE21438, C257SE21633

Reexamination Certificate

active

08008136

ABSTRACT:
A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

REFERENCES:
patent: 6342410 (2002-01-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6562718 (2003-05-01), Xiang et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6770516 (2004-08-01), Wu et al.
patent: 6800885 (2004-10-01), An et al.
patent: 6842048 (2005-01-01), Krivokapic et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 6853020 (2005-02-01), Yu et al.
patent: 6855990 (2005-02-01), Yeo et al.
patent: 6936882 (2005-08-01), Ahmed et al.
patent: 6995438 (2006-02-01), Ahmed et al.
patent: 7091068 (2006-08-01), Ahmed et al.
patent: 7230287 (2007-06-01), Anderson et al.
patent: 7358121 (2008-04-01), Chau et al.
patent: 7537985 (2009-05-01), Anderson et al.
patent: 2003/0102518 (2003-06-01), Fried et al.
patent: 2003/0113970 (2003-06-01), Fried et al.
patent: 2003/0141525 (2003-07-01), Nowak
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2004/0038435 (2004-02-01), Wieczorek et al.
patent: 2004/0048424 (2004-03-01), Wu et al.
patent: 2004/0113171 (2004-06-01), Chiu et al.
patent: 2004/0217420 (2004-11-01), Yeo et al.
patent: 2004/0256647 (2004-12-01), Lee et al.
patent: 2005/0037558 (2005-02-01), Gong et al.
Digh Hisamoto et al., “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-Pending U.S. Appl. No. 10/653,226, filed Sep. 3, 2003, entitled “Fully Silicided Gate Structure for Finfet Devices”.

Affiliated with

Also associated with

Rating

Fully silicided gate structure for FinFET devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fully silicided gate structure for FinFET devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully silicided gate structure for FinFET devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2633940