Fully self-aligned method for fabricating transistor and memory

Details Fully self-aligned method for fabricating transistor and memory Fully self-aligned method for fabricating transistor and memory

1999-04-16

2001-02-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S300000

Reexamination Certificate

active

06190958

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103507, filed Mar. 8, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the fabrication of forming a transistor and a memory, and more particularly to a fully self-aligned method for fabricating a transistor used to manufacture a dynamic random access memory (DRAM).
2. Description of the Related Art
Transistors are the most widely used semiconductor device in integrated circuits. A transistor is usually used as a digital switch for logic circuits and memory devices.
Memory, the semiconductor device for storing information and data, has various types as follows: mask read only memory (Mask ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, static random access memory (SRAM) and dynamic random access memory (DRAM). DRAM is a type of high-density integrated circuit on a silicon chip widely used in the electronic industry for storing digital information.
FIG. 1
is a schematic, cross-sectional view showing a DRAM cell. Referring to
FIG. 1
, a DRAM cell is composed of a gate
101
, source/drain regions
105
and
107
, and a contact pug
109
of the source/drain region for contacting bit lines
111
and capacitor
103
. The source/drain region
105
and bottom electrode
115
of the capacitor
103
contact each other. There are no contact regions between the staggered word line
113
and bottom electrode
115
. If the capacitor
113
is formed below the bit line
111
, then it is called a bit line over capacitor (BOC). If the capacitor
113
s formed above the bit line
111
, then it is called a capacitor over bit line (COB). The semiconductor manufacturers try to improve the shape and size of the capacitor for increasing capacitance of the capacitor. The COB device is widely accepted by manufacturers as a way to form different capacitor shapes in a designated space.
FIGS. 2A
to
2
D are schematic, cross-sectional views showing the conventional method for manufacturing a DRAM capacitor. Referring to
FIG. 2A
, a substrate
202
having gates
204
,
206
,
208
and
210
, and source/drain regions
212
,
214
and
216
, is provided, wherein the gates are covered by spacer
218
. A dielectric layer
220
is then formed on the surface of the entire substrate
102
, through a chemical vapor deposition process, to a thickness of from 500 Å to 2000 Å (angstrom).
Next, referring to
2
B, contact openings
222
and
224
for the source/drain regions are formed in the dielectric layer
220
, exposing surfaces of the substrate
202
by a conventional photolithography process for removing portions of the dielectric layer
220
with respect to contact openings.
Thereafter, referring to
2
C, a conductive layer
230
, formed of polysilicon or tungsten silicide, is formed on the substrate
202
and fills the contact opening
222
and
224
to form conductive plugs
226
and
228
by a chemical vapor deposition. A bit line is formed after the processes of photolithography and etching. A dielectric layer
232
, composed of silicon oxide, is formed on the substrate
202
by a chemical vapor deposition.
Referring to
FIG. 2D
, photolithography and etching processes are used to remove the dielectric layers
220
and
232
located above the source/drain region
214
in sequence for forming a contact opening
233
to expose source/drain regions
214
. Another conductive layer
234
, a bottom electrode of the capacitor, is then formed on the dielectric layer
232
and fills the contact opening
233
to electrically contact the source/drain region
214
. Dielectric layer
236
and top electrode
238
of the capacitor can be formed in the subsequent processes to complete the manufacture of the DRAM cell. The conductive layers
234
and
230
are staggered with respect to each other and have no electrical contact.
The conventional method described above has the drawback of shifting of the contact opening caused by the misalignment of the photolithography process due to the process sequence of forming gates followed by the formation of the contact openings of the source/drain regions. The shifting of the contact opening minimizes the contact areas between the plug and substrate and raises the resistance.
FIG. 6
is a schematic, cross-sectional view showing a partial enlargement of the plug
226
shown in FIG.
2
D. The contact areas between the plug
226
and source/drain region
216
is shrunk because of a misalignment; hence the resistance is raised.
Furthermore, a poly pad with large surface is utilized in other conventional method for increasing the contact areas.
FIG. 7
is a schematic, cross-sectional view showing the structure of a conventional poly pad. Referring to
FIG. 7
, the poly pad is used to increase the contact areas of the plug
226
for solving the problem of misalignment. However, the additional poly pad complicates the manufacturing processes and increases the cost.
SUMMARY OF THE INVENTION
The invention provides a fully self-aligned method for fabricating a transistor. The source/drain contact opening is formed in the formation step of the gate to avoid the problem of misalignment. Therefore, the complex processes and the poly pad layer of the conventional method are not needed.
The invention provides a fully self-aligned method for fabricating memory. The memory cell and logic circuit regions have the same height during the formation process of the memory.
The invention also provides a fully self-aligned method for fabricating a transistor. The method comprises the steps of providing a semiconductor substrate, then subsequently forming a first dielectric layer on the substrate. After that, a plurality of source/drain region contact openings and word line trenches are formed on the first dielectric layer simultaneously by patterning the first dielectric layer. A doped conductive layer is formed in the source/drain contact openings and word line trenches to form a plurality of source/drain conduct plugs and first gate conductive layers, respectively. Thereafter, the first gate conductive layers are removed to expose the substrate. A thermal oxidation is performed to form a gate oxide layer on the exposed substrate and to form a plurality of source/drain regions at the interface between the source/drain contact openings and substrate. A second conductive layer is formed in the word line trenches to form a plurality of second gate conductive layers on the gate oxide layer, wherein the second gate conductive layers have a height less than a depth of the word line trenches. Thereafter, an insulation layer is formed on the substrate and filling the word line trenches.
The invention provides a fully self-aligned method for fabricating memory. The method comprises the steps of providing a semiconductor substrate having a column and row directions, then subsequently forming a first dielectric layer on the substrate. After that, the first dielectric layer is patterned for forming a plurality of source/drain contact openings and a plurality of word line trenches, wherein the word line trenches are parallel to the column direction. A doped conductive layer is formed in the source/drain contact openings and the word line trenches to form a plurality of source/drain contact plugs and a plurality of first word lines, respectively. The first word lines are removed to expose the substrate. A thermal oxidation is patterned to form a gate oxide layer on the exposed substrate and to form a source/drain region at the interface between the source/drain contact plugs and substrate. A first conductive layer is formed on the gate oxide layer within the word line trenches to form a plurality of second word lines, wherein the second word lines are smaller in height than the word line trenches. A first insulation layer is formed on the substrate. A secon

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