Fully isolated dielectric memory cell structure for a dual...

Details Fully isolated dielectric memory cell structure for a dual... Fully isolated dielectric memory cell structure for a dual...

2001-12-20

2003-10-28

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S329000, C257S314000, C257S327000, C438S212000

Reexamination Certificate

active

06639271

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to flash memory cell devices and more specifically, to improvements in dielectric memory cell structures for dual bit storage and a process for making the improved dielectric memory cell structure.
BACKGROUND OF THE INVENTION
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO
2
), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate increases the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a “read” of the memory cell, the magnitude of the current flowing between the source and drain at a predetermined control gate voltage indicates whether the flash cell is programmed.
More recently dielectric memory cell structures have been developed. A conventional dielectric memory cell
10
is shown in cross section in FIG.
1
and is characterized by a vertical stack of an insulating tunnel dielectric layer
12
, a charge trapping dielectric layer
14
, an insulating top oxide layer
16
, and a polysilicon control gate
18
positioned on top of a crystalline silicon substrate
15
. Within the substrate
15
are a channel region
17
positioned below the vertical stack and source diffusion
19
and drain diffusion
23
on opposing sides of the channel region
17
. This particular structure of a silicon channel region
22
, tunnel oxide
12
, nitride
14
, top oxide
16
, and polysilicon control gate
18
is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell
10
is programmed by inducing hot electron injection from the channel region
17
to the nitride layer
14
to create a non volatile negative charge within charge traps existing in the nitride layer
14
. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate
18
. The high voltage on the control gate
18
inverts the channel region
17
while the drain-to-source bias accelerates electrons towards the drain region
23
. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region
17
and the tunnel oxide
12
. While the electrons are accelerated towards the drain region
23
, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region
13
that is close to the drain region
23
(or in a source charge storage region
11
that is close to the source region
19
if a source to drain bias is used) from which the electrons were injected. As such, the SONOS device can be used to store two bits of data, one in each of the charge storage regions
11
and
13
, per cell and are typically referred to as dual bit SONOS devices.
A problem associated with dual bit SONOS structures is that the trapped charge in the drain and source charge storage regions
13
and
11
has a finite spatial distribution that peaks at the drain region
23
and source region
19
respectively and a portion of the charge distribution will spread into the area between the source charge storage region
11
and the drain charge storage region
13
. The spread charge effects the threshold voltage during the read cycle. The charge that accumulates between the source charge storage region
11
and the drain charge storage region
13
is difficult to remove utilizing the hot hole injection erase mechanism. Additionally, charge spreading become more problematic over the lifetime of operation of the device. Each program/erase cycle, may cause further spread of electrons into the area between source charge storage region
11
and the drain charge storage region
13
. The problem is further compounded by the continued decrease in the size of the semiconductor devices, which calls for nitride layers with less area separating the two charge storage regions
11
and
13
.
A need exists in the art for a dual bit memory cell structure which does not suffer the disadvantages discussed above.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide a dual bit dielectric memory cell that comprises a substrate with a source region, a drain region, and a channel region positioned there between. A multilevel charge trapping dielectric is positioned on the surface of the substrate over the channel region and a control gate is positioned on the surface of the multilevel charge trapping dielectric. The multilevel charge trapping dielectric includes a tunnel layer adjacent to the substrate that may comprise a dielectric material with a very low hydrofluoric acid etch rate. The multilevel charge trapping dielectric also includes a top dielectric layer adjacent to the control gate of a second dielectric material selected from the group consisting of an aluminum oxide compound, a Hafnium oxide compound, and a zirconium oxide compound. Such materials may comprise Al
2
O
3
, HfSiO
x
, HfO
2
, and ZrO
2
.
A charge trapping layer is positioned between the tunnel layer and the top dielectric layer and includes a source charge trapping region and a drain charge trapping region separated by an isolation barrier, that may be an oxide, there between. The charge trapping layer may have a thickness range from about 50 A to 100 A in thickness.
The source charge trapping region and the drain charge trapping region may be comprised of a nitride compound such as a material selected from the group consisting of Si
2
N
4
and SiO
x
N
4
. The source charge trapping region and the drain charge trapping region may each have a lateral width beneath the top dielectric layer from about 300 A to 500 A.
A second aspect of the present invention is to provide a method of storing data in dual bit dielectric memory cell, the method comprising: a) utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region; b) utilizing a drain-to-source bias in the presence of a control get field to inject a charge into a drain charge trapping region; and c) providing an isolation barrier between the source charge trapping region and the drain charge trapping region.
A third aspect of the invention provides a method for making the dielectric memory cell structure, including steps of providing a semiconductor substrate; sequentially depositing on the substrate a first dielectric materi

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