Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-23
2003-01-07
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000, C438S230000, C438S284000, C438S592000, C438S596000
Reexamination Certificate
active
06504210
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a fully encapsulated metal-containing damascene gate that is useful as a field effect transistor (FET) in Gigabit dynamic random access memory (DRAM) devices. The present invention also relates to methods of manufacturing the fully encapsulated metal-containing damascene gate which allow the use of a high temperature sidewall gate oxidation step.
BACKGROUND OF THE INVENTION
The present processing of DRAM structures and other like memory structures employs a polysilicon/metallic silicide, such as polysilicon/WSiX, stack as the gate conductor. Gate conductors having a polysilicon/metallic silicide stack typically have a minimum sheet resistivity of about 10 ohms/square or more. Although the resistivity of a polysilicon/metallic silicide stack is suitable for some memory device applications, Gigabit DRAM applications require a much lower resistivity of the gate structure. This requirement has prompted a recent move to gate structures in which the metal silicide is replaced by an elemental metal.
A major problem of using metal-containing gates in Gigabit DRAM applications is that low temperature processing, typically less than 900° C., is required to prevent diffusion of the elemental metal into the surrounding material layers of the gate structure. Working against this is the fact that a good bird's beak oxidation at temperatures higher than 900° C. is needed at the gate edges to provide a low leakage DRAM transfer array device. The above temperature requirements drive a very small process window for gate stacks containing a metal gate.
In prior art DRAM processes, it is also well known that gate polysilicon reactive-ion etching (RIE) damage adversely affects DRAM retention and that support performance is a strong function of the gate stack of the DRAM array (since high temperature post gate stack processing steps adversely affect the support device).
In view of the drawbacks mentioned hereinabove with prior art DRAM processes, there is a continued need for developing a new and improved process in which metals can be used in place of metallic silicides in a gate structure without exhibiting any of the aforementioned problems.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of manufacturing a low resistivity damascene gate for use in high density Gigabit DRAM architectures.
Another object of the present invention is to provide a damascene metal gate that has a high retention associated therewith.
A further object of the present invention is to provide a damascene metal gate that has a low leakage associated therewith.
A still further object of the present invention is to provide a self-aligned damascene metal gate for sub 8F
2
vertical transfer devices.
A yet further object of the present invention is to provide a damascene metal gate having a low aspect ratio which allows for low temperature post gate stack processing and a high performance DRAM support device.
These and other objects and advantages are achieved in the present invention by providing methods wherein a damascene gate is formed such that the metal conductor of the damascene gate is encapsulated by polysilicon and oxide. The inventive methods allow for high temperature gate sidewall oxidation for a good bird's beak at the gate edges, while maintaining a low aspect ratio for low temperature post gate stack processing to ensure a high performance DRAM support device.
Specifically, in one embodiment of the present invention, the inventive method comprises the following processing steps:
(a) providing a semiconductor structure comprising at least one gate hole formed in a gate stack, said gate stack including at least a pad oxide layer and a pad nitride layer being formed on a surface of a substrate, said gate hole having a sacrificial oxide layer located on a bottom portion thereof and sacrificial spacers located on said sacrificial oxide layer;
(b) forming a threshold voltage control region in said substrate;
(c) removing said sacrificial spacers and said sacrificial oxide layer from said gate hole so as to expose a portion of said substrate;
(d) forming a gate oxide layer on said exposed portion of said substrate;
(e) forming a recessed gate polysilicon layer in said gate hole on said gate oxide layer;
(f) forming polysilicon spacers on said recessed gate polysilicon layer;
(g) forming a barrier layer in said gate hole and on said pad nitride layer;
(h) forming a recessed metal layer in said gate hole on said barrier layer;
(i) forming a cap oxide layer in said gate hole on said recessed metal layer; and
(j) removing said barrier layer and said pad nitride layer surrounding said gate hole so as to form a gate structure in which said recessed metal layer is completely encapsulated by polysilicon and oxide.
In an optional, but preferred embodiment of the present invention, the exposed polysilicon sidewalls of said gate structure provided in step (j) above are subjected to an oxidation step.
In another embodiment of the present invention, the gate polysilicon layer formed in step (e) is not recessed. In that embodiment of the present invention, the gate polysilicon layer is formed on the pad nitride layer surrounding said gate hole as well as in the gate hole, and during step (j) above, the polysilicon layer surrounding the gate hole is removed. Alternatively, in this embodiment of the present invention, the polysilicon layer and barrier layer may be recessed below the pad nitride layer prior to forming the recessed metal layer. Additionally, when a non-recessed gate polysilicon layer is employed, oxide spacers are optionally present in the structure.
It is noted that after conducting the various processing steps of the present invention including the optional oxidation step, conventional post gate stack processing steps can be employed so as to form a structure in which the inventive damascene gate is present therein.
The above methods provide a damascene gate structure in which the metal layer is completely encapsulated by polysilicon and oxide. Specifically, in one embodiment of the present invention, the damascene gate structure of the present invention comprises:
a substrate having a gate oxide layer formed on a surface portion of said substrate;
a gate polysilicon layer formed on said gate oxide layer;
a metal layer formed on said gate polysilicon layer;
a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers.
In one embodiment of the present invention, the inventive damascene gate structure includes outer polysilicon layers that are oxidized.
In another embodiment of the present invention, the damascene gate structure includes polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein. Optional oxide spacers formed on the barrier layer are also contemplated herein.
In yet another embodiment of the present invention, the gate structure is formed inside a trench that abuts a vertical transistor region and the metal layer forms a butted contact to the vertical transistor gate polysilicon.
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Divakaruni Ramachandra
Gambino Jeffrey Peter
Mandelman Jack A.
Sardesai Viraj
Weybright Mary Elizabeth
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