Fully dry post-via-etch cleaning method for a damascene process

Details Fully dry post-via-etch cleaning method for a damascene process Fully dry post-via-etch cleaning method for a damascene process

2000-05-12

2001-11-27

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S597000, C438S738000, C430S314000, C430S329000, C430S330000, C156S345420, C156S922000, C156S922000

Reexamination Certificate

active

06323121

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the formation of copper interconnective metallization by a damascene process.
(2) Background of the Invention and Description of Related Art
Integrated circuits are manufactured by forming discrete semiconductor devices in the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into the openings. A conductive layer is applied over the insulating layer and patterned to form wiring interconnections between the device contacts, thereby creating a first level of basic circuitry. The circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with conductive via pass throughs. Depending upon the complexity of the overall integrated circuit, several levels of wiring interconnections are used.
A method for forming the interconnection layer is the damascene process, whereby openings and trenches, comprising an image of the interconnection pattern are formed in an insulative layer. A metal layer is then deposited into the openings and over the insulative layer. Finally, the metal is polished back to the insulative layer leaving the metal pattern inlaid within the insulative layer. Polishing back of the metal layer is accomplished by CMP (chemical mechanical polishing), a relatively old process which has found new application in planarization of insulative layers and more recently in the damascene process. In a single damascene process a metal line pattern is generated which connects to subjacent vias or contacts. In a dual damascene process, both vias/contacts and an interconnective wiring pattern are formed by a single metal deposition and CMP. A description of both single and dual damascene processes may be found in Chang, C. Y. and Sze, S. M., “ULSI Technology” McGraw-Hill, N.Y., (1996), p444-445 and in El-Kareh, B., “Fundamentals of Semiconductor Processing Technologies”, Kluwer, Boston(1995), p563-4. The dual damascene process has been particularly favored for the manufacture of integrated circuits using copper metallurgy. Copper is rapidly replacing aluminum as the metallurgy of choice in integrated circuit manufacturing because it has a higher conductivity than aluminum. The use of copper results in greatly improved circuit performance.
In dual damascene processing, the deep via openings are first partially patterned with a first photoresist mask. Then, using a second photoresist mask, the shallower metal interconnective wiring channels are etched as the vias openings are etched to completion. Often, etch stop layers are used to limit the etching at both the deep and shallow levels. Dai, et.al., U.S. Pat. Nos. 5,877,075 and 5,882,996 show methods for etching both levels using a single photoresist layer, which is patterned twice. Silicon nitride is typically used as an etch stop.
In order to further improve circuit performance, low dielectric constant (low-k) insulative materials have been incorporated into the dielectric layers of modern integrated circuits. These materials provide a lower capacitance than conventional silicon oxide and consequently, an increase in circuit speed. Lou, et.al., U.S. Pat. No. 5,916,823 shows a method for forming a dual damascene structure using a low-k SOG (spin-on-glass). SOGs are alcohol soluble siloxanes or silicates which are spin deposited and baked to drive off solvents resulting in a relatively porous silicon oxide structure. Other porous silica structures such as xerogels have been developed, notably by Texas Instruments Inc. and incorporated into dual damascene processes to obtain insulative layers with dielectric constants as low as 1.3. This is to be compared with a dielectric constant of about 4 for conventional silicon oxide. Other organic and quasi-organic materials such as polysilsesquioxanes and polyarylene ethers have been added to the growing family of low-k and ultra low-k insulative materials. The materials are deposited either by spin-on deposition or by CVD (Chemical vapor deposition).
Although these materials offer welcome improvement in circuit performance, they also pose problems in processing. Because they are very porous, they are not only prone to absorb and retain contaminants, in particular moisture and solvents, but they also react to a large extent with wet processing chemistries such as those used for cleaning and removing residues left after plasma etching and photoresist stripping. In Dai, solvents are removed by baking and a cap oxide liner is deposited on the walls of the etched damascene openings to seal the SOG surfaces against contamination. Whereas Dai uses an oxygen ashing process followed by wet stripping with H
2
SO
4
, H
2
O
2
, and NH
4
OH to remove photoresist and other residues after the via etch such treatment would be damaging to OSOGs (organic spin-on-glasses) and some other low-k insulative materials including those deposited by CVD.
Jeng, U.S. Pat. No. 5,453,157 teaches an anisotropic, low temperature (−40° C. to 20° C.), oxygen plasma ashing process which does not harm the exposed edges of low-k OSOG underlayers. The ashing plasma is made directional with respect to the wafer by biasing the wafer to attract the positively charged oxygen species. In addition, the wafer must be cooled during the ashing, for example by liquid nitrogen.
Fujimura, et.al., U.S. Pat. No. 5,773,201 teaches another photoresist ashing process wherein ashing takes place in a chamber located downstream of an oxygen plasma source. It is shown that hydrogen or water vapor, added to the oxygen plasma, lowers the activation energy of the ashing process. However, hydrogen addition, even in small amounts, creates an explosion hazard. The addition of nitrogen or water vapor to the oxygen plasma increases the ashing rate by increasing the concentration of oxygen atoms in the plasma.
Jain, et.al., U.S. Pat. No. 5,741,626 teaches the use of Ta
3
O
5
as an insulative ARC (anti-reflective coating) and etch stop material for forming dual damascene structures. The insulative property is advantageous when the ARC is used other than directly beneath the photoresist layer, for example between the two main dielectric layers of the dual damascene structure. Ta
2
O
5
reduces the reflectivity of a subjacent aluminum layer by about a factor of 5.
Porous doped silicates such as fluorinated and carbon doped silicate glasses and totally organic, non silicaceous, materials such as fluorinated polyarlyene ethers, are seeing an increased usage in semiconductor processing technology because of their favorable dielectric characteristics and ease of application. These materials are, however, particularly susceptible to etch erosion and contamination from wet etchant and stripping chemistries which have heretofore not been particularly problematic. Complex polymeric residues often result from the reactions of dry etchant components and a variety of organic and inorganic (primarily silicaceous), materials exposed during plasma etching. CVD deposited fluorinated silicate glasses and carbon doped silicates are also susceptible to erosion and contamination by wet etchants.
In addition, wet etchant chemistries also cause damage to exposed copper surfaces which are exposed in certain copper damascene via processes wherein the wet etch clean is used after copper is exposed at the base of the via openings. These residues may no longer be removed by conventional wet etching because of the interaction of the wet etchants with exposed low-k dielectric layers. Oftentimes, for reasons of design or process integration, the edges of low-k dielectric layers, cannot be sealed in the manner of Lou, '823, to pr

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