Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-14
2002-10-22
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06468892
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor production. More precisely the invention relates to improved protection of semiconductor die bonds.
BACKGROUND OF THE INVENTION
To facilitate discussion
FIG. 1
is a front side view of a bump device
100
such as a flip chip, used in the prior art. The bump device
100
may comprise a die
102
, with a plurality of solder bumps
108
mounted thereon.
FIG. 2
is a cross sectional view of the bump device
100
mounted on a substrate
103
. The die
102
may have a plurality of aluminum bond pads
104
. A passivation layer
105
may be patterned around the aluminum bond pads. An under bump metal (UBM), such as a nickel, copper, etc. may be patterned on the aluminum bond pads
104
to improve bump reliability. Solder bumps
108
may be formed on the UMB and reflowed to mechanically and electrically connect the die
102
to the substrate
103
. Thermal stress created by different coefficients of expansion between the die, substrate, and solder bumps may create cracks in the solder bumps near the UMB. In the prior art, after the die
102
is mounted to the substrate
103
an underfill material may be applied between the die
102
and substrate
103
and around the solder bumps
108
to reduce cracks created by thermal stress. Such underfill techniques may require the placement of underfill with each individual die
102
mounted on a substrate
103
. Providing underfill individually to each individual die
102
may be expensive and time consuming, and may require accuracy in dispensing the underfill. The substrate
103
may be mounted to a circuit board
107
using a ball grid array. In such ball grid array (BGA) mounts, a solder mask
110
may be placed on a side of the substrate
103
and patterned to expose bond pads
112
. A pad coating
114
may be placed over the bond pads
112
. Solder bumps
116
may be connected to the pad coating
114
. The solder mask
110
may be an organic material, which may be patterned using photo resist. The solder mask
110
may include liquid photo imagable materials. Solder masks are described in U.S. Pat. No. 4,666,821, entitled “Photopolymer For Use As A Solder Mask”, by Hein et al. incorporated by reference. In the prior art, such solder masks may be applied to a substrate upon which a die is mounted as described in U.S. Pat. No. 5,796,586, by Lee et al. incorporated by reference or on circuit boards to protect the solder lines. Such solder masks may also be applied to circuit boards to protect solder wiring. For direct chip attach, the bump device is mounted directly to a PC board, so that the PC board is the substrate.
It is desirable to provide protection from thermal stress between a die and a substrate that is less expensive and easier and faster to apply.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a variety of techniques for providing a protective layer for providing an improved flip-chip are described. Generally, chips are created as part of a wafer, wherein each chip has bond pads on a front side of the wafer. A patterned mask layer is patterned over the front side of the wafer, so that the patterned mask layer provides apertures over the bond pads. Electrically conductive connectors are formed on each of the bond pads, so that the patterned mask layer is in contact with at least a quarter of the electrically conductive connector. The chips are then singulated.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
REFERENCES:
patent: 4666821 (1987-05-01), Hein et al.
patent: 5796586 (1998-08-01), Lee et al.
patent: 5903058 (1999-05-01), Akram
patent: 6075290 (2000-06-01), Schaefer et al.
patent: 6075710 (2000-06-01), Lau
patent: 6077765 (2000-06-01), Naya
patent: 6228687 (2001-05-01), Akram et al.
patent: 6249044 (2001-06-01), Kao et al.
patent: 6268114 (2001-07-01), Wen et al.
patent: 6281106 (2001-08-01), Higdon et al.
patent: 6312974 (2001-11-01), Wu et al.
Baker Mark Harrison
Kelkar Nikhil
Beyer Weaver & Thomas LLP
Ho Hoai
National Semiconductor Corporation
Tran Long K.
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