Fringing field induced localized charge trapping memory

Details Fringing field induced localized charge trapping memory Fringing field induced localized charge trapping memory

2008-05-20

2008-05-20

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S326000, C257S900000

Reexamination Certificate

active

11175417

ABSTRACT:
The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is substantially orthogonal, multi-portion dielectric layer is formed on the gate and a portion of the silicon layer. Charge trapping dielectrics are attached on the multi-portion dielectric layer acting as carrier trapping structure. The gate-to-source/drain non-overlapped implantation is capable of storing multi-bits per transistor.

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