FPGA powerup to known functional state

Details FPGA powerup to known functional state FPGA powerup to known functional state

2007-12-04

2007-12-04

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S038000, C326S040000

Reexamination Certificate

active

11371833

ABSTRACT:
A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

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