Four transistor SRAM cell with improved read access

Details Four transistor SRAM cell with improved read access Four transistor SRAM cell with improved read access

2000-08-30

2001-08-14

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S203000, C365S207000, C365S230060

Reexamination Certificate

active

06275433

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to a static random access memory (SRAM) cell and sensing circuitry yielding an improved read access time.
2. Description of the Related Art
In many computer systems, high speed redundant memories are commonly used to store recently used data or data that will likely be needed very soon. These memories are referred to as cache memories. A cache memory mirrors data stored in the main memory of the computer system, but because of its significantly higher speed, the cache memory may supply data more quickly. Typically, dynamic random access memories (DRAMs) are used as main memory devices due to their relatively high densities. Cache memories are typically static random access memories (SRAMs). SRAMs generally have lower densities than DRAMs, but they are significantly faster. Because of their higher speeds of operation, SRAMs find additional application in various computer systems, and their use as cache memories is simply one example of their application.
Various configurations of SRAM memory cells have been designed and developed to reduce the silicon area consumed by the cells, to increase the operating speed of the devices, and to achieve numerous other goals. Traditionally, SRAMs have been designed with either four transistors and two polysilicon load resistors, or six transistors, using two PMOS devices as active load devices. Reduction of silicon area consumed by an SRAM cell, i.e., increasing the density of cells in an SRAM device, can be realized by using cells with as few transistors as possible. In many stand-alone SRAM applications, polysilicon load resistors have replaced the PMOS load transistors in the six-transistor cells. Resistive load inverters, however, have very asymmetrical switching transients and have steady-state standby DC power dissipation. Accordingly, many SRAMs embedded in microprocessors have continued to use the six-transistor cells. Other SRAM designs have also been proposed. For example, U.S. Pat. No. 6,011,726, issued Jan. 4, 2000, entitled “Four Device SRAM Cell With Single Bit Line,” describes a cell having four transistors and one polysilicon load resistor. Other approaches have used only four transistors and have relied upon the sub-threshold leakage of the transfer devices in place of load resistors or transistors. These types of cells have been referred to as “loadless” four-transistor CMOS SRAM cells with no polysilicon resistor.
FIG. 1
illustrates a conventional CMOS SRAM cell
10
in combination with a cross-coupled sense amplifier
20
. The cell
10
is coupled to the sense amplifier
20
by way of a bit line
58
and a complementary bit line
60
. The cell
10
includes two NMOS transistors
32
,
34
and two resistors
36
,
38
. The transistor
32
and the resistor
36
are coupled in series between a power supply voltage
42
and a ground potential
44
. The transistor
34
and the resistor
38
are also coupled in series between the power supply voltage
42
and the ground potential
44
. The gate terminal of the transistor
32
is coupled to a node
48
between the transistor
34
and the resistor
38
, and the gate terminal of the transistor
34
is coupled to a node
46
between the transistor
32
and the resistor
36
. An access transistor
52
couples the node
46
of the cell
10
to the complementary bit line
60
, and an access transistor
54
couples the node
48
of the cell
10
to the bit line
58
. An access signal will be provided on line
56
when the cell
10
is to be coupled to the bit line
58
and the complementary bit line
60
so that a datum stored in the cell
10
may be read by way of the sense amplifier
20
. The cell
10
is a symmetrical SRAM cell.
The sense amplifier
20
includes two NMOS transistors
62
,
64
and two PMOS transistors
66
,
68
. The transistor
62
and the transistor
66
are coupled in series between a power supply voltage
42
and a ground potential
44
, and the transistor
64
and the transistor
68
are coupled in series between the power supply voltage
42
and the ground potential
44
. The gate of the transistor
62
is coupled to a node
72
between the transistors
64
and
68
, while the gate of the transistor
64
is coupled to a node
70
between the transistors
62
and
66
. The node
72
of the sense amplifier
20
is coupled to the bit line
58
, while the node
70
of the sense amplifier
20
is coupled to the complementary bit line
60
. When the datum in the cell
10
is to be read, the bit line
58
and the complementary bit line
60
are each pre-charged to a value of approximately one-half the full power supply voltage, or VDD/2. A datum is represented by one of two possible states in which the cell
10
may be maintained. For example, a logical “zero” may be represented in the cell
10
when the node
46
is at or near the ground potential and the node
48
is at or near the power supply potential. A logical “one” might be indicated by the node
48
being at or close to the ground potential and the node
46
being at or close to the power supply potential.
For purposes of explanation, assume the cell
10
stores a logical “one,” meaning the node
48
is at or near the ground potential and the node
46
is at or near the power supply potential. Because the cell
10
is symmetrical, sensing a logical “one” or logical “zero” will require the same amount of time. After the bit line
58
and the complementary bit line
60
have been pre-charged to approximately one-half the power supply potential (by circuitry not shown), an access signal is provided on the line
56
to turn on the access transistors
52
and
54
to couple the nodes
46
and
48
to the complementary bit line
60
and the bit line
58
, respectively. Because the node
48
is at a low potential, the transistor
32
is in an “off,” or non-conducting, state, and because the node
46
is at a high potential, the transistor
34
is in its “on,” or conducting, state. When the nodes
46
and
48
are coupled to the complementary bit line
60
and the bit line
58
, respectively, the conducting transistor
34
will begin to pull the potential on the bit line
58
toward the ground potential. Conversely, because the transistor
32
remains in a non-conducting, or essentially non-conducting, state, the potential on the complementary bit line
60
is pulled up toward the power supply potential through the resistor
36
. As a differential voltage appears between the bit line
58
and the complementary bit line
60
, the sense amplifier
20
will amplify the difference and drive the bit line
58
to ground potential and the complementary bit line
60
to the power supply potential. Output circuitry (not shown) will utilize the potential on the bit line
58
or the potential on the complementary bit line
60
, or both, to produce an output signal indicative of the datum stored in the cell
10
.
FIG. 2
illustrates a read operation on a conventional SRAM cell
100
using single-sided sensing when the bit lines are pre-charged to a high potential (rather than VDD/2). The cell
100
in
FIG. 2
is identical to the cell
10
in FIG.
1
. But, the cell
10
in
FIG. 1
is coupled to a two-input sensing amplifier, whereas the sensing amplifier in
FIG. 2
is single-sided. Depending on the state of the memory cell
100
, either transistor
102
or transistor
104
will be conducting while the other is not conducting. When a transfer device (e.g., transistor
118
) is activated to read the cell
100
, the bit line is initially at a high potential, and if the transistor
104
in the cell is in a conducting state, it pulls the bit line toward ground potential. In the example of
FIG. 2
, the signal on the line
126
to the sense amplifier is in reality only single-sided, or single-ended. The signal is not differential and, as such, is more susceptible to common mode noise.
The present invention is directed to memory cells, as well as sensing and output circuitry, that

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