Four state token passing alignment fault state circuit for micro

Details Four state token passing alignment fault state circuit for micro Four state token passing alignment fault state circuit for micro

1997-10-30

1999-11-09

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

711201, G06F 1100

Patent

active

059833700

ABSTRACT:
A token passing structure controls alignment fault generation. An alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. If the token is present in a particular latch, then the corresponding state is active. If the token is absent, then the corresponding state is inactive. The presence of the token in a predetermined one of the four states causes a fault gate qualifier signal to be active permitting fault generation on address misalignment. Absence of the token from that state causes the fault gate qualifier signal to be inactive prohibiting fault generation on address misalignment. This structure efficiently implements address misalignment fault control by means of token location. Every token location is accessible at every privilege level. An additional instruction not previously supported by Intel microprocessors and Intel compatible microprocessors permits the application program access to the individual token locations and thus to all the permitted states.

REFERENCES:
patent: 5568624 (1996-10-01), Sites et al.
patent: 5596717 (1997-01-01), Marshall, Jr.
patent: 5666508 (1997-09-01), Marshall, Jr.
patent: 5742755 (1998-04-01), Hervin
patent: 5761491 (1998-06-01), Circello et al.

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