Forming minimal size spaces in integrated circuit conductive lin

Details Forming minimal size spaces in integrated circuit conductive lin Forming minimal size spaces in integrated circuit conductive lin

1997-12-05

1999-07-27

Chaudhuri, Olik

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Polycrystalline semiconductor

438532, 438635, H01L 213205, H01L 21324

Patent

active

059306599

ABSTRACT:
A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

REFERENCES:
patent: 4084986 (1978-04-01), Aoki et al.
patent: 4280854 (1981-07-01), Shibata et al.
patent: 4601778 (1986-07-01), Robb
patent: 5270236 (1993-12-01), Rosner
patent: 5677242 (1997-10-01), Aisou

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