Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-05
2001-02-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S637000, C438S639000, C438S670000, C438S671000, C438S673000
Reexamination Certificate
active
06191034
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to fabricating integrated circuits and, more specifically, to fabricating the conductive line levels of integrated circuits with minimal size spaces.
BACKGROUND OF THE INVENTION
With the demand for higher levels of integration of semiconductor chips, such as silicon semiconductor chips, and the need for greater density in these circuits, the conductive line dimensions and spaces between the conductive lines of the integrated circuits become more and more critical. This is especially the case with a microprocessor integrated circuit chip of which a large portion of the real estate of the chip is an SRAM. For increased performance of future microprocessors, the storage capacity of the SRAM must increase thereby requiring a larger portion of real estate of the microprocessor.
A limit on the dimensions in the integrated circuits is the resolution of the optical lithographic system used in the fabrication of the integrated circuit including the conductive line levels. Today, with deep ultra violet photolithography, the resolution limit is about 0.25 microns. To break through this barrier, semiconductor manufactures are resorting to techniques like phase shift lithography, which require expensive masks but permit optical lithography to achieve these small line widths, and X-ray lithography which is extremely costly from an exposure equipment and mask making standpoint. Electron beam is another exposure alternative to achieve line widths of less than 0.25 microns, but its throughput is extremely slow when it is used in a direct write mode.
Techniques are thus required to reduce the line widths without resorting to expensive masks or exposure equipment and permit the use of conventional optical lithography.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an integrated circuit with minimal line widths with conventional optical lithography.
Another object of the present invention is to provide an integrated circuit fabrication method in which the gaps or spaces between conductive lines can be further reduced after being first defined by optical lithography.
A further object of the present invention is to provide a fabrication method of an integrated circuit which uses conventional semiconductor manufacturing apparatus.
In accordance with the present invention, a semiconductor material, such as a silicon wafer, is formed with a conductive line pattern, such as polysilicon, using conventional optical lithography. To form a gap or space in the conductive line pattern, an etch protective layer, such as silicon nitride, is preferably disposed on the conductive line pattern followed by an insulating layer, such as silicon oxide, disposed on the etch protective layer. Again using conventional optical lithography, a pattern opening is formed in the insulating layer and the preferable etch protective layer, by preferably exposure and development of an optical resist and anisotropic dry etching. With the opening formed in the insulating and etch protection layer, a layer of conformal material is deposited on insulating layer and on the walls of the insulating and etch protective layers. This conformal layer is anisotropically etched to create sidewalls in the opening with the gap or space between the sidewalls being the desired gap or space in the conductive line. Again using anisotropic dry etching with a gas having greater selectivity for the conductive line material than the conformal material, a gap or space is etched in conductive line which is two sidewall spacer widths less in dimension than the original opening, thereby being able to achieve a gap or space less than the resolution of the optical lithography.
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Holst John C.
Horne Stephen C.
Kepler Nicholas J.
Klein Richard K.
Lee Raymond T.
Advanced Micro Devices
Foley & Lardner
Niebling John F.
Zarneke David A.
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