Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-25
2002-04-23
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S622000, C438S687000
Reexamination Certificate
active
06376363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique of forming a copper interconnection on a semiconductor wafer.
2. Description of the Related Art
In manufacturing a semiconductor device such as an IC (Integrated Circuit), an LSI (Large Scale Integrated Circuit) or the like, there are normally taken the steps of forming an insulating film on the surface of a semiconductor wafer such as a silicon wafer or the like, and thereafter forming, thereon, a photoresist patterned into a prescribed shape and carrying out the etching of the insulating film, using the photoresist as a mask. A trench or a hole required for formation of an interconnection, an interlayer via plug or such is formed through the steps of this sort.
Now, the formation of an insulating film and a metal film for an interconnection is performed over the entire surface of the wafer at a time so that these films are formed even in the area close to the wafer edge that is not utilized for chips. If the metal film and the insulating film are left behind in such an area, the peeling-off of the film may take place during the subsequent manufacturing steps, and, consequently, the contamination of the wafer and manufacturing apparatus may be brought about.
Further, the formation of the photoresist is also performed over the entire surface of the wafer, but the exposure for the resist is not applied to the area close to the wafer edge. As a result, in the case that a positive resist is used, the resist remains in the vicinity of the wafer edge even after the development. This remaining resist may cause the peeling-off of the film or the like, while transferring and holding the wafer, which leads to the contamination of the adjacent apparatus and the wafer surface and, consequently, a lowering of the production yield.
To overcome this problem, after the photoresist is formed and patterned into a prescribed shape, the step of removing the photoresist in the vicinity of the wafer edge is carried out. This prevents the contamination by the photoresist that is left in the vicinity of the wafer edge. Moreover, with the resist in the vicinity of the wafer edge being taken away, the insulating film and the like in this area can be removed by etching so that the contamination caused by the peeling-off of the insulating film and the like can be prevented.
When a positive resist is employed, the step of removing the photoresist in the vicinity of the wafer edge is normally carried out by means of peripheral exposure. That is, in addition to the exposure applied to the pattern formation region, the peripheral exposure of the wafer is performed to remove the unnecessary resist lying in the peripheral area. The peripheral exposure of the wafer is made, for example, while rotating the wafer that is coated with a resist so as to achieve the exposure of a ring-shaped neighbouring area of the wafer edge.
FIG. 17
is a top plan view of a semiconductor wafer and, by the peripheral exposure, a wafer edge neighbouring area
50
is exposed and then removed by means of dissolution in a later step. Meanwhile, an unexposed area
51
including element formation regions remains, thereat, without being removed by dissolution. Further, the peripheral exposure can be performed along the whole circumference of the wafer or only a part of the wafer edge.
FIG. 18
is a series of schematic cross-sectional views showing the steps of a manufacturing method including the step of peripheral exposure. These steps are described below. Firstly, after a silicon oxynitride film
2
and a silicon oxide film
3
are formed, in this order, over an element formation layer
1
in which an element such as a transistor or the like is formed, a coating of a photoresist material is applied thereto and then dried (FIG.
18
(
a
)). Next, through a mask patterned into a prescribed shape, an element formation region is subjected to exposure, whereby unexposed sections
4
a
and exposed sections
4
b
are formed therein (FIG.
18
(
b
)). Subsequently, performing peripheral exposure, the silicon oxide film in the vicinity of the wafer edge (shown on the left side of the drawing) is made an exposed section
4
b
(FIG.
18
(
c
)). After these exposures are made, the exposed sections
4
b
are removed by dissolution with a chemical solution. FIG.
19
(
a
) shows the state after this removal is made. Now, using the photoresist
4
as a mask, dry etchings are carried out, whereby the silicon oxide film
3
is first removed and then the silicon oxynitride film
2
is removed. In etching these films, appropriate etching gases are used, respectively. FIG.
19
(
b
) shows the state after the etchings are completed. After that, by ashing and a wet treatment with a resist peeling-off agent, the photoresist
4
is removed (FIG.
19
(
c
)). Through the steps described above, there reaches the state in which the silicon oxide film
3
and the silicon oxynitride film
2
in the vicinity of the wafer edge are removed.
Next, referring to
FIGS. 10
to
14
, a conventional forming method of copper interconnections including the above steps of peripheral exposure is described below. Firstly, after a silicon oxynitride film
2
and a silicon oxide film
3
are formed, in this order, over an element formation layer
1
in which an element such as a transistor or the like is formed (FIG.
10
(
a
)). In each drawing, there are shown an element formation region
25
and a wafer edge neighbouring region
26
. The term a “wafer edge neighbouring region”
26
as used herein denotes a ring-shaped region along the wafer edge where no element formation is made. As against this, an “element formation region”
25
indicates a region that is situated inside of the wafer edge neighbouring region
26
and sectioned into with scribe lines. The wafer edge neighbouring area
50
and an area
51
including element formation regions have the positioning relation, for example, as shown in FIG.
17
.
Next, a coating of a photoresist material is applied thereto and then dried. Next, through a mask patterned into a prescribed shape, an element formation region
25
is subjected to exposure, and then peripheral exposure is applied to the wafer edge neighbouring region
26
. After these exposures are made, the exposed sections are removed by dissolution with a chemical solution. FIG.
10
(
b
) shows the state after this removal is made. Now, using the photoresist
4
as a mask, dry etchings are carried out, whereby the silicon oxide film
3
is first removed and then the silicon oxynitride film
2
is removed. In etching these films, optimum etching gases are used, respectively. By these etchings , a trench for an interconnection is formed in the element formation region
25
and, at the same time, an insulating film and the like in the wafer edge neighbouring region
26
are removed. FIG.
10
(
c
) shows the state after the etchings are completed. After that, by ashing and a wet treatment with a resist peeling-off agent, the photoresist
4
is removed.
Next, after a Ta (tantalum) film
5
is grown over the entire surface by the sputtering method, a copper film
6
is grown by the electroplating method, the CVD (Chemical Vapour Deposition) method or the like. (FIG.
11
(
a
)). After these films are grown, superfluous portions of the copper film
6
and the Ta film
5
are removed, by polishing, using the CMP (Chemical Mechanical Polishing) so as to form a damascene interconnection (buried-type interconnection). In the vicinity of the wafer edge (the left end in the drawing), hereat, some of the copper film
6
and the Ta film
5
are left behind in a stepped part and polishing remains are generated (FIG.
11
(
b
)).
Next, after a silicon oxynitride film
7
is grown over the entire surface of the wafer by the plasma CVD method or the like, a silicon oxide film
8
is grown by the plasma CVD method (FIG.
12
(
a
)). Next, after a coating of a photoresist material is applied thereto and then dried, the exposure for patterning of the element formation region as well as the peripher
Elms Richard
McGinn & Gibb PLLC
Smith Brad
LandOfFree
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