Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-09
2002-04-16
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S304000, C257S532000, C257S534000, C438S239000, C438S233000, C438S234000
Reexamination Certificate
active
06373083
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a structure and fabrication method of a capacitor which has variable capacitance in accordance with an electrode connection.
2. Description of the Conventional Art
FIG. 1
is a diagram illustrating a structure of a conventional capacitor.
As shown therein, a semiconductor substrate
100
consists of an active region
101
and an isolation region
102
on which a field oxide film
102
a
is formed by a local oxidation of silicon (LOCOS) process. A gate oxide film
103
is formed on the active region
101
of the semiconductor substrate
100
and a gate electrode
104
is formed thereon. A source/drain
104
a is formed in the semiconductor substrate
100
at both sides of the gate electrode
104
. A lower electrode
105
of a capacitor C is formed on the isolation region, that is, the field oxide film
102
a
and a dielectric film
106
and an upper electrode
107
are sequentially formed on the lower electrode
105
, the lower and upper electrodes
105
and
107
being formed of polysilicon. Further, an insulating film
108
is formed over the gate electrode
104
and an entire surface of the capacitor C and contact holes
109
are respectively formed in the insulating film
108
on predetermined portions of the upper electrode
107
and the source region
104
a
. Conductive plugs
110
are filled in the contact holes
109
, the conductive plugs
110
being connected to each other by a conductive wire
111
.
As shown in
FIG. 1
, the capacitance of the conventional capacitor is proportional to an area in which the upper and lower electrodes face to each other and a dielectric constant of the dielectric film. However, the conventional capacitor has disadvantages as follows.
That is, since the capacitor is formed on the field oxide film having a step difference which is higher than that of the active part, the step difference between the level of the field oxide film and the active region becomes large after fabricating the capacitor, which affects a planarization in the semiconductor device fabrication process.
In addition, as the integration of the semiconductor device increases, a dimension of the field oxide isolation region becomes smaller and accordingly the capacitance is decreased. Thus, in the conventional capacitor, the area occupied by the semiconductor substrate is unavoidably enlarged to increase the capacitance, thereby impeding the high-integration of the semiconductor device.
Further, since the conventional capacitor has the predetermined capacitance, a complicated circuit must be additionally provided to change the capacitance of the capacitor and thus the number of patterns applied on the semiconductor substrate increases, which results the hindrance of the high-integration of the semiconductor device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a structure and fabrication method of a capacitor which obviates the problems and disadvantages in the conventional art.
An object of the present invention is to provide a capacitor that improves a step difference between a field oxide film and an active region to obtain planarized surface in a semiconductor device fabricating process and thereby improve the reliability of the semiconductor device.
Another object of the present invention is to provide a capacitor that obtains capacitance which is higher than a conventional capacitor with the same area.
Another object of the present invention is to provide a capacitor that varies capacitance in accordance with user's intention without adding a complicated circuit.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a capacitor which includes a bottom electrode formed in a device isolation region of a semiconductor substrate, a first dielectric film formed on the bottom electrode, a middle electrode formed on the first dielectric film, a second dielectric film formed on the middle electrode, and a top electrode formed on the second dielectric film.
Here, the capacitor is formed on the semiconductor substrate having a trench in which an insulating film is filled and the bottom electrode is buried in the insulating film. In addition, two of the top, bottom and middle electrodes is applied with the same voltage.
Also, to achieve the above objects of the present invention, there is provided a fabrication method of a capacitor, which includes forming a trench on a semiconductor substrate, forming a first insulating film having a predetermined thickness in the trench, forming a first conductive layer pattern on the first insulating film, forming a second insulating film pattern on the first conductive layer pattern, forming a second conductive layer pattern on the second insulating pattern, forming an insulating film pattern on the second conductive layer pattern, and forming a third conductive layer on the insulating film pattern.
REFERENCES:
patent: 5770876 (1998-06-01), Lam et al.
patent: 5959326 (1999-09-01), Aiso et al.
patent: 6015729 (2000-01-01), Shirley et al.
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
Wojciechowicz Edward
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