Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-09-27
2005-09-27
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000, C438S700000, C438S715000, C438S719000
Reexamination Certificate
active
06949467
ABSTRACT:
The present invention provides a manufacturing method of a contact for use in a semiconductor device and a manufacturing method of a PMOS device using the same, which can obtain an electrical characteristic of a low contact resistance similar to a mixed implantation of49BF2+ions and11B+ions and reduce a manufacturing cost. The method for forming a contact of a semiconductor device includes: the steps of: forming an insulating layer on a conductive semiconductor layer; forming a contact hole within the insulating layer to expose a portion of the conductive semiconductor layer; forming a plug implantation region by implanting30BF+ions into the exposed conductive semiconductor layer disposed on a bottom of the contact hole; performing an annealing process for activating dopants injected by the implantation of30BF+ions; and filling the contact hole with a conductive layer.
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patent: 02-32344 (2002-05-01), None
Dong-Ho Lee, et al.;High quality shallow p+ −n junction formation by employing BF2/low energy11B mixed ion implant process; 0-7803-4538-X/99$10.00; 1999 IEEE; pp. 83-86.
Yong-Sun Sohn, et al;BF2+/11B+ Mixed Ion Implantation for P+ Shallow Junction Formation;Fabrication and Characterization of Advanced Materials; 1995; pp. 1087-1092.
Hynix / Semiconductor Inc.
Mayer Brown Rowe & Maw LLP
Norton Nadine G.
Tran Binh X.
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