Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-12
2001-11-20
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S271000, C438S272000, C257S332000, C257S333000
Reexamination Certificate
active
06319776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming semiconductor devices, and more particularly relates to a method for fabricating devices having an enhancement in high current drive capability and a diminishment in the area occupied by devices.
2. Description of the Prior Art
Given the present developments and changes in technology, integrated circuits (ICs) are gradually moving toward an ultra-high density target. Therefore, there is a trend toward the gradual diminishment in semiconductor device sizes and distances between devices. Thus, no matter how tiny devices integrated become, it is still very important to maintain the best operating condition within the devices. Conventional structures of high voltage CMOS (HV-CMOS) devices have channels and drift regions in the horizontal direction, which results in a larger chip area occupation. Therefore, a better and more advanced method for fabricating devices is needed urgently.
FIG. 1A
shows a cross-sectional view of a structure of a conventional CMOS transistor. The structure comprises a p-type conductivity substrate
10
, a N
+
source electrode
11
, a N
+
drain electrode
12
, a drift region
13
, a field oxide (FOX) layer
14
, a gate oxide layer
15
, and a gate electrode
16
.
In the structure of a conventional CMOS transistor described above, channel and drift regions are all the in horizontal direction and only source and drain electrode are located inside the substrate. This type of structure makes channel and drift regions of CMOS seems shorter in length. When the channel of CMOS device shrinks in length, hot carrier effects become more serious. There are many ways to solve hot carrier effects for short channel length CMOS devices. Wherein the simplest method is to reduce CMOS transistor's operating voltage. For example, 5V is reduced to 3.3V or even 2.5V, this reduces the channel's horizontal electric field and results in an ability to form any hot carrier. Although the phenomena of “carrier multiples” can be greatly reduced, the device would not be able to be used under high voltage operations. If it is desired to avoid reducing the operating voltage for CMOS transistors and also to solve hot carrier effects for short channel length CMOS devices, then the channel length of CMOS devices need to be increased. The structure in horizontal direction and an increase in the channel length would all occupy a greater chip area, which is against the trend of gradual diminishment of size in semiconductor devices.
Another method that is popular in solving hot carrier effects for short channel length CMOS devices is placing an N− type region with lower doping density at the place where the source/drain region draws near the channel. This kind of design has been called “Lightly Doped Drain”, or LDD. The use of LDD is not a perfect solution. First of all, LDD makes CMOS fabrication more complicated. Next, due to the lower doping density of LDD, the series resistance between the source and drain would be higher. This causes a reduction in the device's operating speed and an increment in power dissipation.
SUMMARY OF THE INVENTION
The main objective of the present invention is to provide a method for fabricating high voltage semiconductor devices having a gradient doping for the drift regions that substantially enhanced the device's current drive capability and its breakdown voltage. In addition, according to the present invention, spacer oxide is used to act as the point of exertion for the edges of polysilicon gate in avoiding breakdown voltage from occuring in advance. Moreover, change the geometrical placement of device's channel and drift regions is changed from the conventional horizontal direction to vertical direction, which results in a greater reduction in the occupied chip area.
The present invention relates to a method for forming of a transistor device, where the resulting structure of the present invention is shown in FIG.
1
B. Firstly, a p-type semiconductor substrate
100
is provided, followed by the forming a first trench
140
within the substrate. Next, a pair of source (
200
,
130
, and
120
) and drain (
210
,
131
, and
121
) region are formed just right beside the first trench
140
.
Within the pair of source and drain region, there is formed a first doping region
120
and
121
. Also, within the same pair of source and drain region, there is formed a second doping region
130
and
131
that is directly above the first doping region. The pair of source and drain regions is not completed without the formation of a third doping region
200
and
210
, which is directly above the second doping region.
The method for fabricating the device further comprises the formation of a second trench
170
and follows a spacer
160
formation on top of a sidewall of the first trench
140
, and also occupies a portion of the bottom of the first trench. A gate oxide layer
180
is formed on the top of both sidewalls and the bottom surface of the second trench
170
. And finally, a buried gate electrode is formed on top of the gate oxide layer and also fills up both the first trench and the second trench.
The method for fabricating the special structure of the present invention mentioned above comprises the following advantages. First of all, a trench etching method is used to place a gate electrode and spacers and also to change the geometrical placement of device's channel and drift regions from horizontal direction to the vertical direction, all of those making a contribution to a greater reduction in the occupied chip area.
Secondly, the channel length increases in relation to the formation of the gate electrode by a trenching method. Hot carrier effects would be reduced in a great proportion due to this extension in the channel length.
Thirdly, in the field of source/drain doping density, if the first doping region and the second doping region have the same doping density and both are low, the device is capable of handling high voltages but its current drive capability is weaker. If the first doping region and the second doping region have same doping density and both are high, the device is not capable in handling high voltages but its current drive capability is stronger. Therefore, the present invention uses different doping densities, from low to high, to form a complementary structure in solving the above defects and also for lifting the breakdown voltage.
Finally, the placement of spacers in the present invention can avoid breakdown voltage from occurring in advance, that is to make sure that the topper upper layers will not breakdown before lower layers.
REFERENCES:
patent: 4830975 (1989-05-01), Bovaird et al.
patent: 5559357 (1996-09-01), Krivokapic
patent: 5736435 (1998-04-01), Venkatesan et al.
patent: 5888880 (1999-03-01), Gardner et al.
patent: 5937297 (1999-08-01), Peidous
patent: 6133606 (2000-10-01), Tung
patent: 6201278 (2001-03-01), Gardner et al.
Chaudhuri Olik
Rao Shrinivas H.
United Microelectronics Corp.
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