Forming electronic structures having dual dielectric...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S244000, C438S386000

Reexamination Certificate

active

06566191

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to semiconductor devices, and more particularly, to a method of forming semiconductor devices having dual dielectric thicknesses, and the devices so formed.
2. Related Art
Currently, semiconductor devices are being constructed that are capable of performing several different functions, each potentially operating at different voltage levels. As a result, both thick and thin oxide dielectric layers are required to accommodate the passage of high and low voltages, respectively. For instance, thin oxide dielectric layers, capable if withstanding low voltages, are necessary to maintain high speed operation of the device, and perform such functions as memory storage, etc. However, the thin dielectric material is incapable of safely accommodating the higher voltages, as required to perform such functions as capacitance decoupling, low to high and high to low signal interfacing, electrostatic discharge protection, etc.
Accordingly, there is a need in the industry to efficiently construct a semiconductor device capable of safely accommodating both high and low voltages, while maintaining a small overall device size.
SUMMARY OF THE INVENTION
The first general aspect of the present invention provides electronic structure comprising: a first device and a second device formed within a substrate, wherein the first device includes a first dielectric and the second device includes a second dielectric, and wherein the second dielectric has a greater thickness than the first dielectric.
The second general aspect of the present invention provides a method of forming an electronic structure, comprising: providing a substrate; forming a first device having a first dielectric thickness; and forming a second device having a second dielectric thickness, wherein the second dielectric thickness is greater than the first dielectric thickness.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.


REFERENCES:
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4641279 (1987-02-01), Kimura et al.
patent: 4651306 (1987-03-01), Yanagisawa
patent: 4912535 (1990-03-01), Okumura
patent: 4931849 (1990-06-01), Tajima
patent: 5275974 (1994-01-01), Ellul et al.
patent: 5708559 (1998-01-01), Brabazon et al.
patent: 5776817 (1998-07-01), Liang
patent: 5818110 (1998-10-01), Cronin
patent: 6214686 (2001-04-01), Divakaruni et al.
patent: 6297103 (2001-10-01), Ahn et al.
patent: 63-199456 (1988-08-01), None
patent: 1-119057 (1989-05-01), None
patent: 6-5809 (1994-01-01), None
“Method to Make Wide Lines Thicker Without an Added Photo Mask”, Cronin et al. IBM TDB, Jun. 1990, vol. 33 No. 1A, pp. 460-461.
“Chemical Vapor Deposition of Tungsten to Fill Oversize Vias”, J. E. Cronin, IBM TDB, Dec. 1986, vol. 29, No. 7, pp. 3254-3255.
“Variable Depth Contact Hole Preparation Utilizing a Nucleation Layer and Selective Chemical Vapor Deposition for Stud Formation”, Cronin et al. IBM TDB, Jun. 1986, vol. 29, No. 1, pp. 310 311.
“Optical Thickness Monitor for Continuous Vapor Deposited Film”, Cronin et al., IBM TDB, Aug. 1986, vol. 29, No. 3, pp. 1306-1307.
Extending Trench Dram Technology To 0.15 &mgr;m Groundrule And Beyond, Rupp et al., IEDM 99, pp. 33-36.
A Fully Planarized 0.25 &mgr;m CMOS Technology For 256Mbit DRAM and Beyond, Bronner et al., 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 15-16.
A 0.6&mgr;m2256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), Nesbit et al., IEDM 93, pp. 627-630.

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